Senior Staff Engineer, SoC Architecture – Memory Subsystem and Interconnect

Samsung Research America; Mountain View (CA); On-site; USD 272,489,280 - 408,596,160; Full time

Job summary

Samsung Research America is seeking a Senior Staff Engineer to lead architecture of memory subsystem and interconnect in next-generation SoCs. The role combines fabric, system cache and DRAM controller design with performance and power tradeoffs across workloads.

You will guide architectural decisions, perform high-level modeling, and collaborate with silicon bring-up, software and hardware teams to deliver validated features for high-performance Galaxy-class devices.

Qualifications

• 12+ years of SOC/ASIC design and architecture experience.
• Deep memory subsystem and memory controller know‑how.
• Experience with fabric/interconnect architectures and QoS.
• Familiarity with JEDEC standards (LPDDR, DDR, HBM) is a plus.

Responsibilities

• Guide development of Fabric, System cache and DRAM controller features to boost performance and power efficiency.
• Propose architectures for next‑gen SOCs across new and existing markets.
• Evaluate proposals with cross‑functional teams and communicate results to SW/HW/Leadership.
• Perform high‑level performance modeling and analysis for workloads and benchmarks.
• Lead studies to justify architecture in microarchitecture with performance/area/power tradeoffs.
• Deliver architecture specs to design teams and articulate across audiences.
• Collaborate with silicon bring‑up and product teams to verify delivered performance.

Skills

SOC/ASIC design

Memory controller architecture

Fabric/Interconnect

Performance modeling

ARM ACE/AXI/AHB

Power optimization

JEDEC LPDDR/DDR/HBM

Education

Bachelor's/Master's/PhD in CS/Engineering

Tools

BookSim Simulator

Platform Architect

Job description

Senior Staff Engineer, SoC Architecture – Memory Subsystem and Interconnect

The Samsung Research America SOC Architecture Lab provides innovative SoC architecture, bus / memory subsystem, multimedia subsystems and key IP blocks for future Samsung Galaxy products (Smartphones, tablets and future devices). We are defining the high-performance SoC architecture development for various Galaxy device lineups. This lab collaborates with Samsung’s strategic SoC partners, Samsung MX headquarter team, and key R&D teams around the globe to innovate and reinvent technology that will positively impact millions of people around the world via the Galaxy flagship products.

We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to help architect next generation SOCs. This is a highly visible hands‑on role leading individual and team contributions to Fabric, System cache and DRAM controller sub‑system architecture, interface, performance and power tradeoffs.

Position Responsibilities

• Guide on development of innovative Fabric, System cache and DRAM controller Architectural and microarchitectural features to boost power and performance on various targeted workloads in next generation SOCs
• Identify and deliver Fabric, System cache and DRAM controller subsystem architecture proposals for products in new and existing markets
• Evaluate architecture proposal benefits in collaboration with team of SoC Architects and communicate the results across related engineering audiences (SW, HW, Architecture, Leadership)
• Perform high-level performance modeling/simulation and analysis of Fabric, System cache and DRAM controller features, applications, benchmarks, and complex uses cases
• Direct and orchestrate performance modeling, and studies to support inclusion of these features in the next generation “Fabric, System cache and DRAM controller” microarchitecture based on performance, area or power improvement
• Deliver architecture/microarchitecture proposals and specifications to the design team and articulate them effectively across audiences ranging from hardware & software engineers to architecture community peers, and to technology leadership
• Collaborate with silicon bring‑up and product teams to verify and debug the proposal and its delivered performance
• Collaborate across teams to bring microarchitectural proposals to fruition across the SOC, Driver, OS, System through detailed documentations

Required Skills

• BSc, Masters, or PhD in Computer Science/Engineering, or equivalent combination of education, training, and experience
• 12+ years of experience in SOC or ASIC design and architecture
• Prior direct experience (> 9 years) in Fabric, System Cache, DRAM controller Architecture or microarchitecture is required
• Understanding of memory controller architecture, memory scheduling, prioritization and QoS
• Detailed knowledge of ARM bus infrastructure (ACE/AXI/AHB)
• Fluid knowledge of one or more JEDEC standards such as LPDDR, DDR, or HBM, and the ability to analyze such standards and drive recommendations
• Background in memory systems and computer architecture to understand the tradeoffs among memory bandwidth, latency, performance, power, SoC area

Special Attributes

• Experience with BookSim Simulator
• Experience with Platform Architect

Compensation

Hourly Pay Rate Range

$197,800 - $296,600 USD

Essential Job Functions

This position will be performed in an office setting. The position will require the incumbent to sit and stand at a desk, communicate in person and by telephone, and frequently operate standard office equipment, such as telephones and computers.

Equal Employment Opportunity

Samsung Research America is committed to employing a diverse workforce, and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

For more information regarding protection from discrimination under Federal law for applicants and employees, please refer to Pay Transparency.