Senior Silicon CPU Architect - Performance & Architecture

Google Inc.; Town of Texas (WI); Hybrid; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Job summary

Google is hiring a Senior CPU Architecture and Performance Architect, Silicon, to push the boundaries of custom silicon for consumer devices. You will influence architecture choices and drive performance and efficiency gains across real hardware implementations.

You will interact with design and verification teams, write architecture specs, and develop micro-benchmarks to ensure pre- and post-silicon performance targets are met.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 8 years of experience with micro-processor architecture, micro-architecture, performance, and design.
• Experience with performance modeling, analysis, correlation, and workload characterization and experience with CPU architecture (e.g., CPU block).

Responsibilities

• Plan and evaluate ARM’s architecture features from architecture and performance perspectives.
• Develop a performance model for analysis and microarchitecture studies.
• Lead collaboration with design and verification teams to develop efficient CPU implementation.
• Define and write CPU subsystem architecture specifications.
• Drive performance correlation between the model and RTL implementation, including micro-benchmark development and pre-/post-silicon performance triage.

Skills

CPU Architecture

Performance Modeling

Micro-processor Design

Education

Bachelor’s degree in EE/CE/CS or related field

Job description

Google is hiring a Senior CPU Architecture and Performance Architect, Silicon, to push the boundaries of custom silicon for consumer devices. You will influence architecture choices and drive performance and efficiency gains across real hardware implementations.

You will interact with design and verification teams, write architecture specs, and develop micro-benchmarks to ensure pre- and post-silicon performance targets are met.