Senior CPU Architect: Performance & Microarchitecture Lead

Google; Mountain View (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google in Mountain View, CA seeks a Senior CPU Architect to drive microarchitecture and performance modeling for next‑gen processors. You will collaborate with RTL, design verification, and software teams to deliver a high‑performance CPU implementation that meets strict power and area targets.

Requires a strong track record in CPU architecture, multi-year experience in microarchitecture, and expertise with ARM/RISC-V/x86 ISA, Linux driver/runtime components.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent.
• 10 years of experience in microprocessor architecture, microarchitecture, performance and design.
• Experience with CPU architecture blocks, performance modeling, correlation, and workload characterization.
• Experience with ISA (ARM, RISC-V, x86) and system software components (Linux, drivers, runtime).

Responsibilities

• Deliver CPU solutions to complex problems including performance, microarchitecture, tooling, and methodology.
• Plan and drive ARM architecture features from architecture and performance angles.
• Define and write CPU subsystem architecture specifications.
• Lead collaboration with RTL, design verification, and physical design for high-performance CPU implementation.
• Drive performance correlation between model and RTL and triage pre-/post-silicon performance issues.

Skills

CPU architecture

Performance modeling

Linux/OS tooling

Education

Bachelor's degree in EE/CS or equivalent

Master's or PhD in relevant field preferred

Job description

Google in Mountain View, CA seeks a Senior CPU Architect to drive microarchitecture and performance modeling for next‑gen processors. You will collaborate with RTL, design verification, and software teams to deliver a high‑performance CPU implementation that meets strict power and area targets.

Requires a strong track record in CPU architecture, multi-year experience in microarchitecture, and expertise with ARM/RISC-V/x86 ISA, Linux driver/runtime components.