Senior CPU Architect — Performance & Microarchitecture

Google; United States; On-site; USD 192,000 - 278,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

Google seeks a Senior CPU Architecture and Performance Architect to own outcomes in CPU architecture, performance modeling, and silicon implementation across multiple US sites. The role involves driving architecture features, collaborating with RTL and design teams, and delivering high-performance CPU designs.

In-person interviews are typical, with preferred locations including Mountain View or Austin. The candidate should have 10+ years in microprocessor architecture, a strong background in ISA

Qualifications

• Bachelor's degree or equivalent practical experience in a related field.
• 10 years of experience in microprocessor architecture, microarchitecture, performance and design.
• Experience with CPU architecture blocks, performance modeling and workload characterization.
• Experience with CPU ISA (ARM/RISC-V/x86) and system software components.

Responsibilities

• Deliver solutions to complex problems that may be ambiguous and/or lacking clear precedent, including CPU performance and microarchitecture design.
• Plan, drive, and evaluate ARM’s architecture features from both architecture and performance angles.
• Define and write CPU subsystem architecture specifications.
• Lead collaboration with RTL, design verification, and physical design teams to develop a high performance and efficient CPU implementation.
• Drive performance correlation between the performance model and RTL implementation and triage pre-silicon and post-silicon performance issues.

Skills

CPU architecture

Performance modeling

System software

ISA knowledge

Education

Bachelor's degree in Electrical Engineering / Computer Engineering / Computer Science

Master's or PhD in Electrical/Computer Engineering or Computer Science

Tools

Linux

Drivers

Runtime environments

Job description

Google seeks a Senior CPU Architecture and Performance Architect to own outcomes in CPU architecture, performance modeling, and silicon implementation across multiple US sites. The role involves driving architecture features, collaborating with RTL and design teams, and delivering high-performance CPU designs.

In-person interviews are typical, with preferred locations including Mountain View or Austin. The candidate should have 10+ years in microprocessor architecture, a strong background in ISA