Senior CPU Architecture and Performance Architect, Silicon

Socket.dev; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Bonus target

Equity

Benefits

Job summary

Google's Devices & Services team pushes boundaries by developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide.

Your expertise will shape the next generation of hardware experiences, delivering performance, efficiency, and seamless integration. Individual pay is determined by factors including job-related skills, experience, and relevant education or training; US range shown

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or Computer Science, or equivalent practical experience.
• 8 years of experience with micro-processor architecture, micro-architecture, performance, and design.
• Experience with performance modeling, analysis, correlation, and workload characterization; CPU architecture knowledge.

Responsibilities

• Plan and evaluate ARM's architecture features from architecture and performance aspects.
• Develop a performance model for performance analysis and microarchitecture studies.
• Lead collaboration with design and verification teams to develop efficient CPU implementation.
• Define and write CPU subsystem architecture specifications.
• Drive performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage.

Skills

CPU architecture

Performance modeling

Workload characterization

Micro-architecture

Education

Bachelor's degree in EE/CE/CS

Master's or PhD in EE/CE/CS (architecture focus)

Job description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with micro-processor architecture, micro-architecture, performance, and design.
• Experience with performance modeling, analysis, correlation, and workload characterization and experience with CPU architecture (e.g., CPU block).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
• 5 years of experience in CPU micro-architecture exploration and development.
• Knowledge of processor instruction set architecture (e.g., ARM, RISC-V, x86).
• Knowledge of system software components, such as Linux, drivers, and runtime.

About the job:

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities:

• Plan and evaluate ARM's architecture features from both architecture and performance aspects.
• Develop a performance model for performance analysis and microarchitecture studies.
• Lead collaboration with design and verification teams to develop efficient CPU implementation.
• Define and write CPU subsystem architecture specifications.
• Drive performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage.