Senior Signal Integrity Engineer - PAM4 SerDes (Onsite)

Hewlett Packard Enterprise

Sunnyvale (CA)

On-site

USD 174,000 - 353,000

Full time

14 days+

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Job summary

Hewlett Packard Enterprise in Sunnyvale, California, is seeking an experienced Signal Integrity Engineer for an onsite role focused on high-speed PAM4 SerDes, channel, and power integrity analyses for cutting-edge networking products. You will collaborate with ASIC vendors, board teams, and test groups to optimize margins and validate SI/PI performance.

This role emphasizes hands-on measurements, model correlations, and creating robust design rules.

Qualifications

Typically, 10+ years of Signal Integrity analysis experience with a bachelor’s degree in Electrical engineering, Computer engineering, Microwave, and/or RF engineering.
Typically, 8+ years of Signal Integrity analysis experience with a master’s degree in Electrical engineering, Computer engineering, Microwave, and/or RF engineering.
Experience with 56G/112G ASIC PAM4 SerDes technologies is required.
200G ASIC PAM4 experience desired.
Hands-on experience in serial channels up to 200G line rates for coefficient tuning, TP1A measurements.

Responsibilities

Perform COM (channel margin analysis) to provide design trade-offs amongst ASIC package, board, and connectors.
Correlate ASIC PAM4 SerDes simulation results with Measurements and work with component and ASIC vendors to improve model accuracy.
Perform PCB timing analysis, work with board engineers and layout designers to implement all design SI rules, develop and document all layout/SI design rules and checklists.
ASIC PAM4 SerDes parametric tuning to improve design margins of serial links.
Perform SIDVT measurements on boards and correlates simulations with DVT measurements.Provide technical assessment of projects to SI management team.