Senior SI/PI Lead for AI Compute Systems

Cerebras Systems; Sunnyvale (CA); On-site; USD 220,000 - 250,000; Full time

Job summary

Cerebras Systems in Sunnyvale, CA is seeking an experienced System Signal Integrity and Power Integrity Engineer Lead to solve complex SI/PI challenges in next-generation AI compute systems. The role emphasizes deep technical analysis across high‑speed interfaces, PDNs, rigid-flex interconnects, and advanced packaging.

The ideal candidate will have 15+ years of system-level SI/PI expertise, a Master’s degree in Electrical Engineering, and a track record of collaboration with silicon and package

Qualifications

• Master’s degree in Electrical Engineering required.
• 15+ years of depth in system-level SI/PI for high-speed hardware systems.
• Experience with chip-to-board interfaces and advanced packaging is essential.

Responsibilities

• Solve complex SI/PI problems for high-speed AI compute platforms, including chip-to-chip and chip-to-board interfaces.
• Perform advanced pre-layout and post-layout SI/PI analysis across PCBs, rigid-flex, and flex assemblies.
• Lead root-cause analysis for margin shortfalls, impedance issues, coupling, and simulation-to-hardware mismatches.
• Analyze SI/PI challenges in flex circuits, high-density interconnects, and advanced packaging tech.
• Analyze and troubleshoot power delivery networks using DC/AC simulations and hardware correlation.
• Define stack-ups and impedance structures to meet performance targets; review schematics and layouts for SI/PI risks.

Skills

High-speed SI/PI analysis

PCB/rigid-flex stack-up

Flex connectors/advanced packaging

2D/3D EM simulation tools

Power delivery network analysis

Transmission line theory/microwave

HW/SI correlation to hardware

Education

Master’s degree in Electrical Engineering

Job description

Cerebras Systems in Sunnyvale, CA is seeking an experienced System Signal Integrity and Power Integrity Engineer Lead to solve complex SI/PI challenges in next-generation AI compute systems. The role emphasizes deep technical analysis across high‑speed interfaces, PDNs, rigid-flex interconnects, and advanced packaging.

The ideal candidate will have 15+ years of system-level SI/PI expertise, a Master’s degree in Electrical Engineering, and a track record of collaboration with silicon and package