Senior IC Package Layout Engineer — 2.5D/3D-IC Focus

Amazon Web Services (AWS); Austin (TX); On-site; USD 136,000 - 184,000; Full time

Job summary

Annapurna Labs (U.S.) Inc. in Austin, TX is seeking a Package Layout Design Engineer to contribute to the physical design of advanced IC packages for ML and data center ASICs.

You will execute package layout tasks from floor planning through tape-out, coordinating with SI/PI, thermal, and manufacturing teams to meet performance, density, and reliability targets. Strong background in 2.5D/3D-IC, RDL, TSV, and OSAT collaboration is preferred.

Qualifications

• BS in Electrical Engineering or related field; strong debugging skills across architecture/algorithms/functionality/performance
• Experience verifying at multiple logic levels from IP blocks to SoCs to full system testing
• 5+ years in IC package layout and physical design
• Experience executing package designs from concept through tape-out for multi-layer substrates or interposers
• Hands-on with package layout tools (Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition)
• Understanding of 2.5D/3D-IC, fan-out WLP, RDL, TSV, microbumps, or silicon bridge interconnects
• Knowledge of layout rules, DFM constraints, and physical verification (DRC, connectivity)
• Experience with bump map/escape routing, power/ground plane design
• Strong communication across design, SI/PI, and manufacturing teams

Responsibilities

• Execute package layout tasks across the design cycle from floor planning to tape out
• Implement physical designs for 2.5D/3D-IC, interposers, and advanced packaging architectures
• Support floorplan development considering die placement, bump maps, and power/ground routing
• Perform RDL and substrate routing for high-density interconnects
• Coordinate with ASIC teams to align die-package interface
• Contribute to cross-level layout co-optimization across die RDL, interposer/substrate, and PCB
• Maintain package stack-up definitions with SI/PI and materials teams
• Run physical verifications (DRC, connectivity) and support design closure
• Refine design rules with OSAT partners and foundries to ensure DFM compliance
• Collaborate with SI/PI engineers on impedance control and shielding

Skills

IC package layout

Physical design

Tape-out

Cadence APD/SiP

Synopsys IC Packaging

Mentor Xpedition

2.5D/3D-IC

RDL routing

OSAT coordination

Power/GND plane design

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical or Communications Engineering

Tools

Cadence APD/SiP

Synopsys IC Packaging

Mentor Xpedition

Job description

Annapurna Labs (U.S.) Inc. in Austin, TX is seeking a Package Layout Design Engineer to contribute to the physical design of advanced IC packages for ML and data center ASICs.

You will execute package layout tasks from floor planning through tape-out, coordinating with SI/PI, thermal, and manufacturing teams to meet performance, density, and reliability targets. Strong background in 2.5D/3D-IC, RDL, TSV, and OSAT collaboration is preferred.