Senior Package Layout Engineer: 2.5D/3D IC Packaging Lead

Amazon Web Services (AWS); Austin (TX); On-site; USD 159,200 - 215,300; Full time

Job summary

Annapurna Labs (U.S.) Inc. is seeking a senior Package Layout Engineer to lead end-to-end physical design of IC packages for next-generation ML and data-center ASICs.

You will own the package layout from floor planning through tape-out, coordinating with silicon, SI/PI, thermal, and manufacturing teams to meet performance, density, and reliability targets. You will drive advanced packaging architectures (2.5D/3D-IC, fan-out WLP) and manage cross-team design validation, DFM compliance, and

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• 10+ years of IC package layout and physical design experience.
• Proven track record leading package designs from concept to tape out.
• Hands-on with Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition.
• Deep understanding of 2.5D/3D-IC, fan-out WLP, RDL, TSV interconnects.
• Familiar with DFM constraints and physical verification methodologies.
• Experience with bump map and high-pin-count layouts.
• Experience collaborating with OSAT partners on NPI and yield.

Responsibilities

• Lead the full package layout cycle from floor planning to tape out release.
• Drive physical design of packaging architectures including 2.5D/3D-IC and fan-out WLP.
• Define and optimize floorplans with power/ground, routing, and decoupling placements.
• Perform detailed RDL/substrate routing for high-density interconnects.
• Coordinate die-level routing with ASIC teams for power delivery and signaling.
• Drive cross-level layout co-optimization across die/interposer/PCB.
• Develop package stack-up definitions with SI/PI and materials teams.
• Create and enforce design rules with OSATs for DFM and yield.
• Run DRC/connectivity checks and drive design closure with zero escapes.
• Manage schedules, milestones, and tape-out Deliverables across projects.
• Collaborate with SI/PI to incorporate electrical constraints into layout.

Skills

IC package layout

Impedance control

PDN design

Mentorship

DRC verification

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree (preferred)

Tools

Cadence APD/SiP

Synopsys IC Packaging

Mentor Xpedition

Job description

Annapurna Labs (U.S.) Inc. is seeking a senior Package Layout Engineer to lead end-to-end physical design of IC packages for next-generation ML and data-center ASICs.

You will own the package layout from floor planning through tape-out, coordinating with silicon, SI/PI, thermal, and manufacturing teams to meet performance, density, and reliability targets. You will drive advanced packaging architectures (2.5D/3D-IC, fan-out WLP) and manage cross-team design validation, DFM compliance, and