Senior SI/PI Engineer – 2.5D/3D Packaging

Amazon Web Services (AWS); Austin (TX); On-site; USD 159,000 - 215,000; Full time

Benefits offered by this job

RSUs

Sign-on bonus

Health insurance

401(k) matching

Career growth

Job summary

Annapurna Labs (U.S.) Inc. is seeking a Sr. Signal & Power Integrity Engineer in Austin, TX to lead the SI/PI analysis for next-generation machine learning and data center ASICs. You will own package-level strategy, work across IC, package, and board teams, and optimize designs for electrical performance and manufacturing yield.

Requirements include 10+ years in SI/PI, strong EM tools experience, and deep knowledge of 2.5D/3D packaging. AWS affiliation with competitive benefits is implied.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 10+ years of signal integrity, power integrity, and package design experience.
• Deep expertise in package SI/PI analysis: S-parameter extraction, PDN impedance, IR drop, crosstalk, and return loss.
• Hands-on experience with EM simulation and SI/PI tools such as HFSS, Cadence Sigrity (PowerSI, PowerDC, Clarity), ADS, or equivalent.
• Strong understanding of advanced packaging technologies: 2.5D/3D-IC, silicon interposers, fan-out wafer-level packaging, RDL, TSVs, and microbump interconnects.
• Proficiency in stack-up design and impedance control for multi-layer organic substrates and silicon interposers.
• Hands-on experience correlating package SI/PI simulations with lab measurements (TDR, VNA, oscilloscope).

Responsibilities

• Lead package-level SI/PI analysis for 2.5D, 3D-IC, fan-out, and interposers.
• Design and optimize package stack-ups and impedance control.
• Perform high-speed channel simulations for die-to-die and die-to-board interfaces.
• Analyze and optimize PDN end-to-end from die bumps to board.
• Characterize on-die capacitance and IPD capacitor effectiveness within PDN.
• Interface with die-level PDN teams to align power requirements.
• Conduct 3D/2.5D EMIR analysis to validate IR drop and EM.
• Model interconnects: microbumps, TSVs, RDL traces for signals and power.
• Apply equalization and evaluate channel margins for PCIe/UCIe links.
• Clock distribution and jitter analysis at package level; manage skew.
• Collaborate with ASIC, board, and packaging teams to optimize architecture.
• Identify manufacturing risks and mitigate impedance variation impacts.
• Develop and maintain package SI/PI modeling flows and guidelines.

Skills

S-parameter extraction

PDN impedance analysis

IR drop analysis

Crosstalk modeling

Return loss analysis

EM simulation

HFSS

Cadence Sigrity

Power integrity

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering (preferred)

Tools

HFSS

Cadence Sigrity PowerSI

Cadence PowerDC

Clarity

ADS

Job description

Annapurna Labs (U.S.) Inc. is seeking a Sr. Signal & Power Integrity Engineer in Austin, TX to lead the SI/PI analysis for next-generation machine learning and data center ASICs. You will own package-level strategy, work across IC, package, and board teams, and optimize designs for electrical performance and manufacturing yield.

Requirements include 10+ years in SI/PI, strong EM tools experience, and deep knowledge of 2.5D/3D packaging. AWS affiliation with competitive benefits is implied.