Senior RTL Power Macromodeling Engineer

Samsungsemiconductor; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Benefits offered by this job

4+ weeks paid time off

Holidays and sick leave

Fertility/adoption stipend

Medical/Dental/Vision/401k benefits

Onsite café and gym

Job summary

Samsung Semiconductor seeks an engineer to develop power and energy macromodels for die-to-die PHY and 2.5D interposer interconnect in C-HBM programs. Models are built from S-parameter interconnect data, calibrated against circuit references, and optimized for long workload traces to feed time-indexed power maps into trace-driven simulations.

The role requires strong Python, S-parameter familiarity, and CMOS power analysis, with onsite presence in San Jose, CA.

Qualifications

• Strong Python for numerical computing.
• Familiarity with S-parameters and frequency-domain analysis.
• Experience with SPICE-level circuit simulation.
• Understanding of dynamic switching power in CMOS drivers.

Responsibilities

• Develop energy and power macromodels from S-parameter models.
• Extract per-lane capacitance and relate to switching energy.
• Create circuit-level SPICE reference to calibrate models.
• Develop reduced-order model forms and compare accuracy.
• Design calibration stimuli and parameter extraction procedures.
• Ensure models run efficiently over wide buses and long traces.
• Analyze sensitivity to data patterns and operating points.
• Extend modeling approach to more interfaces and structures as needed.
• Deliver validated models and regression checks into the simulation pipeline.

Skills

Python for numerical computing

Circuit modeling

Analytical thinking

Verbal communication

Education

Bachelor's degree +5+ years

Master's +3+ years

PhD +0 years

Tools

S-parameter analysis

SPICE-level simulation

RTL/SystemC familiarity

FloTHERM / CFD tools

Job description

Samsung Semiconductor seeks an engineer to develop power and energy macromodels for die-to-die PHY and 2.5D interposer interconnect in C-HBM programs. Models are built from S-parameter interconnect data, calibrated against circuit references, and optimized for long workload traces to feed time-indexed power maps into trace-driven simulations.

The role requires strong Python, S-parameter familiarity, and CMOS power analysis, with onsite presence in San Jose, CA.