RTL Design Engineer — Mixed-Signal DSP Specialist

Apple, Inc.; Cupertino (CA); Presencial; USD 129.000 - 225.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Apple stock programs

Discretionary bonuses

Relocation assistance

Descripción de la vacante

Apple in Cupertino, California seeks a results‑oriented RTL Design Engineer to join our world‑class mixed-signal silicon team. You will design, verify, and bring up digital and signal processing blocks using Verilog/SystemVerilog, while advancing DSP algorithms and high‑performance RTL.

You will collaborate with analog designers, algorithm engineers, and verification specialists to implement features, write meaningful assertions and testbenches, and support lab bring‑up and silicon validation.

Formación

• Bachelor's degree in Electrical Engineering
• Experience in RTL design and verification
• Knowledge of Verilog/SystemVerilog and DSP concepts

Responsabilidades

• RTL Design & Implementation: Develop and optimize RTL code in Verilog/SystemVerilog for mixed-signal digital blocks and signal processing pipelines
• DSP Algorithm Translation: Translate DSP concepts into efficient RTL implementations
• Design Verification: Write assertions and testbenches, participate in functional verification
• Integration & Bring-up: Collaborate with cross-functional teams to integrate IPs and verify performance in silicon
• Collaborative Problem-Solving: Work with analog designers, algorithm engineers, verification specialists, and system architects

Conocimientos

Verilog/SystemVerilog

DSP concepts

RTL algorithm implementation

GenAI in hardware design

Educación

Bachelor's degree in Electrical Engineering

Herramientas

Verilog simulators

Linters

Clock-domain crossing checkers

Perl

Python

Descripción del empleo

Apple in Cupertino, California seeks a results‑oriented RTL Design Engineer to join our world‑class mixed-signal silicon team. You will design, verify, and bring up digital and signal processing blocks using Verilog/SystemVerilog, while advancing DSP algorithms and high‑performance RTL.

You will collaborate with analog designers, algorithm engineers, and verification specialists to implement features, write meaningful assertions and testbenches, and support lab bring‑up and silicon validation.