Senior RTL Design Engineer - SerDes DSP

Credo; San Jose (CA); On-site; USD 130,000 - 200,000; Full time

Benefits offered by this job

Discretionary bonus

Equity

Medical benefits

Job summary

Credo is seeking a PHY RTL Design Engineer to join our mission to transform connectivity at scale. In this role, you will own RTL architecture, design, implementation, and verification of advanced SerDes DSP blocks used in networking, AI, data center, and HPC products.

This position is onsite at our San Jose HQ. The ideal candidate has strong digital design fundamentals, hands-on RTL development experience, and a solid understanding of high‑speed SerDes.

Qualifications

• BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of digital design experience (or equivalent expertise for senior candidates).
• Strong RTL development skills using System Verilog.
• Experience designing high-speed communication or DSP hardware.
• Solid understanding of fixed-point arithmetic RTL implementation.
• Experience with ASIC development flow (e.g., Lint, CDC/RDC, Synthesis, Timing analysis).
• Familiarity with EDA tools from Synopsys, Cadence, or Siemens.
• Strong debugging and problem-solving skills.

Responsibilities

• Define RTL micro-architecture for digital PHY and SerDes DSP functions.
• Develop synthesizable RTL for DSP blocks (FFE, DFE, adaptive equalization, CDR loops).
• Work with system architects and algorithm teams to translate DSP algorithms into RTL.
• Optimize designs for performance, power, area, and latency.
• Verify DSP modules and debug functional issues.
• Support synthesis, timing closure, CDC/RDC analysis, and DFT integration.
• Analyze silicon bring-up data with validation teams to resolve issues.
• Support PHY integration and system-level debugging.

Skills

SystemVerilog

Digital design

RTL development

High-speed SerDes design

Debugging

Timing analysis

Education

BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field

Tools

Synopsys

Cadence

Siemens

Job description

Credo is seeking a PHY RTL Design Engineer to join our mission to transform connectivity at scale. In this role, you will own RTL architecture, design, implementation, and verification of advanced SerDes DSP blocks used in networking, AI, data center, and HPC products.

This position is onsite at our San Jose HQ. The ideal candidate has strong digital design fundamentals, hands-on RTL development experience, and a solid understanding of high‑speed SerDes.