High-Speed SerDes RTL Design Engineer

AMD; San Jose (CA); Hybrid; USD 100,000 - 130,000; Full time

Job summary

A leading semiconductor company based in California is seeking an innovative RTL design engineer to develop high-performance wireline transceivers. The role requires proficiency in digital design, specifically RTL coding with Verilog/System Verilog, along with strong analytical skills and a team-oriented mindset. Key responsibilities include collaborating on high-speed SerDes design and performing various verification tasks. This opportunity is open to applicants across the U.S. who hold a relevant degree in electrical or computer engineering.

Qualifications

• Strong analytical and problem-solving skills.
• Proficient in RTL design and verification.
• Excellent communication and teamwork skills.

Responsibilities

• Collaborate on high-speed SerDes PHY design.
• Design RTL for calibration and adaptation loops.
• Apply low power design techniques.
• Verify functionality using block-level test benches.
• Conduct static timing closure with validation teams.

Skills

Logic design concepts

RTL coding using Verilog/System Verilog

Micro-architecture

Design checker tools

Functional verification tools

Low power design

Mixed signal design

Scripting languages (Python, Perl, TCL)

Education

Bachelor’s or master’s degree in electrical engineering or computer engineering

Job description

A leading semiconductor company based in California is seeking an innovative RTL design engineer to develop high-performance wireline transceivers. The role requires proficiency in digital design, specifically RTL coding with Verilog/System Verilog, along with strong analytical skills and a team-oriented mindset. Key responsibilities include collaborating on high-speed SerDes design and performing various verification tasks. This opportunity is open to applicants across the U.S. who hold a relevant degree in electrical or computer engineering.