Senior RTL Design Engineer - Memory Controller IP

Arm; Austin (TX); Hybrid; USD 198,000 - 268,000; Full time

Job summary

Arm System IP enables designers to build Arm AMBA systems that are high performance, power efficient and reliable. This role focuses on developing memory controller specifications and RTL design for high-end SoCs.

You will collaborate with verification teams, define micro-architecture plans, and ensure RTL quality through linting and synthesis tools. A hybrid work model is in place to balance office and home settings.

Qualifications

• 5+ years in microprocessor/SoC/memory controller and/or interconnect IP design.
• Prior RTL design experience is required.
• Knowledge of DRAM specs (LPDDR5/6, DDR5/6, HBM3/4) and AMBA4/5 bus protocols.
• Experience with Verilog or VHDL and design synthesis.
• Experience with RTL design quality checks (Lint, CDC, Power, Synthesis).

Responsibilities

• Develop memory controller high-level specs and requirements.
• Define and author detailed micro-architecture specifications.
• Develop SystemVerilog RTL for blocks and functions.
• Collaborate with design/verification teams to meet requirements.
• Debug RTL with modern simulation and debug tools.

Skills

Memory controller RTL

AMBA5 CHI

Verilog/VHDL

RTL design

Synthesis & lint

Education

Bachelors or Masters in CS/EE

Tools

Lint

CDC

Power

Synthesis

Job description

Arm System IP enables designers to build Arm AMBA systems that are high performance, power efficient and reliable. This role focuses on developing memory controller specifications and RTL design for high-end SoCs.

You will collaborate with verification teams, define micro-architecture plans, and ensure RTL quality through linting and synthesis tools. A hybrid work model is in place to balance office and home settings.