Senior RTL Design Engineer for Space ASICs

SpaceX; Sunnyvale (CA); On-site; USD 175,000 - 280,000; Full time

Benefits offered by this job

Stock options

Medical, vision and dental coverage

401(k) retirement plan

Paid vacation and holidays

Parental leave

Employee Stock Purchase Plan

Job summary

SpaceX is seeking an experienced Senior RTL Design Engineer (Silicon Engineering) to develop next-generation ASICs for Starlink and space-ground infrastructure. You will work with cross-disciplinary teams on architecture, verification, and integration, delivering fully verified RTL and timing-closed designs.

The role involves close collaboration with verification, physical implementation, and other engineering teams, with emphasis on high-speed, power-efficient design and clock-domain

Qualifications

• Bachelor’s degree in electrical or computer engineering, or computer science.
• 5+ years of RTL implementation experience.
• Experience with RTL verification and timing closure.

Responsibilities

• Evaluate architectural trade-offs based on features and system limits.
• Define micro-architecture and RTL in Verilog/SystemVerilog; deliver verified, synthesis-timing clean design.
• Collaborate with verification team to ensure full coverage of the design.
• Provide timing constraints for IPs and support physical implementation.

Skills

RTL implementation

Verilog/SystemVerilog

ASIC/SoC integration

Embedded CPU subsystems

Scripting (Python)

EDA tools (HDL simulators, HDL Lint)

Clock-domain crossings

Timing closure

Education

Bachelor’s degree in electrical/computer engineering or computer science

Tools

HDL simulators

HDL Lint tools

Synthesis tools

Job description

SpaceX is seeking an experienced Senior RTL Design Engineer (Silicon Engineering) to develop next-generation ASICs for Starlink and space-ground infrastructure. You will work with cross-disciplinary teams on architecture, verification, and integration, delivering fully verified RTL and timing-closed designs.

The role involves close collaboration with verification, physical implementation, and other engineering teams, with emphasis on high-speed, power-efficient design and clock-domain