Senior RFIC & EM Design Engineer

Qualcomm; Santa Clara (CA); On-site; USD 139,400 - 209,200; Full time

Benefits offered by this job

Annual bonus program

RSU grants

Comprehensive benefits

Job summary

Qualcomm is seeking an RFIC Design Engineer in Santa Clara to design and develop RF passive components for next-generation RFICs. You will work with the circuit design team to optimize component sizes and performance, delivering compact models and clean physical designs for 6nm/14ff CMOS and SOI technologies.

The ideal candidate has 3+ years in RF/Analog design, strong EM simulation experience, and proficiency with Cadence/Virtuoso/ADS.

Qualifications

• Bachelor's degree in Electrical Engineering with 3+ years of RF/Analog design experience.
• Master’s degree in Electrical Engineering with 2+ years of ASIC design experience.
• PhD in Electrical Engineering with relevant research or industry experience.
• 2+ years using CADENCE, Virtuoso, or ADS for design/verification.

Responsibilities

• Design and develop RF passive components for next-gen RFICs in 6nm/14ff CMOS and SOI.
• Collaborate with circuit designers to optimize component sizes and performance.

Skills

RF passive design

EM simulation

Cadence tools

Agilent ADS

MoM EM solvers

Education

BSEE in Electrical Engineering

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence

Virtuoso

ADS

Job description

Qualcomm is seeking an RFIC Design Engineer in Santa Clara to design and develop RF passive components for next-generation RFICs. You will work with the circuit design team to optimize component sizes and performance, delivering compact models and clean physical designs for 6nm/14ff CMOS and SOI technologies.

The ideal candidate has 3+ years in RF/Analog design, strong EM simulation experience, and proficiency with Cadence/Virtuoso/ADS.