Senior RFIC Design Engineer - Wireless Transceivers

Qualcomm

San Diego (CA)

On-site

USD 121,000 - 201,000

Full time

14 days+

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Job summary

Qualcomm Technologies, Inc. is seeking an RFIC Design Engineer to define, design, and develop complex RF/Analog circuits for wireless products (4G/5G/6G, WLAN, BT, GPS).

The role involves transistor-level design, circuit topology analysis, and debugging in integration with SoCs and discrete RFICs. You will use Cadence/Virtuoso/ADS for simulations, collaborate across a matrixed organization, and contribute to feature descriptions and documentation while staying aligned with industry trends in

Qualifications

  • Bachelor's degree in Electrical Engineering with 3+ years of experience designing RF/Analog circuits for wireless products and 2+ years of ASIC design/verification or related work experience.
  • Master's degree in Electrical Engineering or related field with 2+ years of ASIC design/verification or related work experience.
  • PhD in Electrical Engineering or related field.

Responsibilities

  • Uses tools/applications to contribute to the architecture and design of one or more small, well-defined blocks based on specifications.
  • Runs simulations to determine circuit performance under various conditions with some supervision.
  • Writes basic test plans and reviews test results to assess performance and identify bugs in own work.
  • Debugs simple issues and escalates complex issues.
  • Writes clear technical documentation and feature descriptions for small projects with some supervision.

Skills

RF/Analog design
ASIC design/verification
Cadence/Virtuoso/ADS

Education

Bachelor's in Electrical Engineering
Master's in Electrical Engineering
PhD in Electrical Engineering

Tools

Cadence
Virtuoso
ADS

Job description

Qualcomm Technologies, Inc. is seeking an RFIC Design Engineer to define, design, and develop complex RF/Analog circuits for wireless products (4G/5G/6G, WLAN, BT, GPS).

The role involves transistor-level design, circuit topology analysis, and debugging in integration with SoCs and discrete RFICs. You will use Cadence/Virtuoso/ADS for simulations, collaborate across a matrixed organization, and contribute to feature descriptions and documentation while staying aligned with industry trends in

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