Senior RFIC Design Lead – High‑Speed Analog & RF

WD; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

WD is seeking an RF/Analog IC Design Engineer to work on high-performance circuitry in San Jose, CA, or Irvine, CA. The role covers transistor- and block-level design, simulation, layout supervision, and verification for cutting-edge storage-system technologies.

You will collaborate with distributed teams, contribute to successful design releases, and leverage Cadence, Mentor, Siemens, and Ansys tools. BS, MS, or PhD in a related field is required.

Qualifications

• Hands-on design and development experience in RF and analog ICs.
• Experience in full CMOS circuit design across baseband, LNAs, mixers, PA, and related stages.
• Experience in 40nm and below CMOS technology.
• Proven track record of design releases and mass production.
• Knowledge of standard EDA tools (Cadence, Mentor, Siemens, Ansys).
• Experience with RF/analog block layout such as LNAs and ADC/DACs.

Responsibilities

• Design high-performance RF and analog circuit blocks.
• Handle transistor, block, and module-level design, simulation, and layout supervision.
• Prepare test plans, assess reliability and yield, and drive test correlations.
• Communicate effectively with cross-functional teams and document results.

Skills

RF design

Analog IC design

CMOS circuit design

LNA/Mixer/UPD/DAC

EDA tools experience

Layout for RF/Analog blocks

Team collaboration

Education

BS, MS or PhD in related field

Tools

Cadence

Mentor

Siemens

Ansys

Job description

WD is seeking an RF/Analog IC Design Engineer to work on high-performance circuitry in San Jose, CA, or Irvine, CA. The role covers transistor- and block-level design, simulation, layout supervision, and verification for cutting-edge storage-system technologies.

You will collaborate with distributed teams, contribute to successful design releases, and leverage Cadence, Mentor, Siemens, and Ansys tools. BS, MS, or PhD in a related field is required.