Senior RFIC Design Engineer – Wireless Transceivers

Socket.dev; San Diego (CA); On-site; USD 134,000 - 201,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking an RFIC-focused engineer in California to define, design and develop complex RFICs and transceivers for wireless standards.

You will analyze signal paths, perform transistor-level design and debug algorithms in hardware, partnering with layout teams to realize integrated circuits. The role requires strong RF/Analog design experience, CADENCE/Virtuoso/ADS proficiency, and a track record in ASIC design/verification, with potential for growth in complex SoC

Qualifications

• Bachelor's degree in Electrical Engineering with 3+ years RF/Analog circuit design and 2+ years ASIC experience.
• Master's degree in Electrical Engineering or related field with 2+ years ASIC design/verification.
• PhD in Electrical Engineering or related field.
• 2+ years using Cadence, Virtuoso or ADS.

Responsibilities

• Contribute to architecture and design of small defined blocks per specs.
• Run simulations to assess circuit performance under various conditions.
• Collaborate with layout engineers to generate layout and perform physical verification.
• Write basic test plans and review results to identify bugs.
• Debug simple issues and escalate complex ones.
• Apply neural networks for circuit optimization and analysis.
• Keep up with RFIC industry trends and contribute ideas.
• Document technical details for small projects.

Skills

RF/Analog circuit design

ASIC design/verification

High-frequency RF concepts

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering or related field

PhD in Electrical Engineering or related field

Tools

Cadence

Virtuoso

ADS

Job description

Qualcomm Technologies, Inc. is seeking an RFIC-focused engineer in California to define, design and develop complex RFICs and transceivers for wireless standards.

You will analyze signal paths, perform transistor-level design and debug algorithms in hardware, partnering with layout teams to realize integrated circuits. The role requires strong RF/Analog design experience, CADENCE/Virtuoso/ADS proficiency, and a track record in ASIC design/verification, with potential for growth in complex SoC