RF/Analog IC Design Engineer for 5G SoCs

Qualcomm; Santa Clara (CA); On-site; USD 168,600 - 252,800; Full time

Job summary

Qualcomm Atheros, Inc. is seeking an RF/Analog IC Design Engineer in Santa Clara to define and develop complex RFICs for 4G/5G and WLAN applications.

You will perform transistor-level design, validate circuits with simulations, and collaborate with layout and test teams to ensure performance targets are met. Applicants should have a degree in Electrical Engineering with several years of ASIC/RF design experience and proficiency in Cadence, Virtuoso, and ADS.

Qualifications

• Bachelor's degree in Electrical Engineering with 3+ years of RF/Analog circuit design experience.
• Experience with RF/Analog blocks for wireless products (LNA, PLL) and 4+ years of ASIC design/verification.
• Strong background in transistor-level design and RFIC layout verification.

Responsibilities

• Lead circuit-level design of complex RFIC blocks aligned to system requirements.
• Run simulations to verify performance across conditions and temperatures.
• Collaborate with layout engineers to ensure proper floorplanning and physical verification.
• Mentor junior engineers and contribute to technical documentation.

Skills

RF/Analog design

LNA design

PLL design

ASIC design

Cadence

Virtuoso

ADS

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence

Virtuoso

ADS

Job description

Qualcomm Atheros, Inc. is seeking an RF/Analog IC Design Engineer in Santa Clara to define and develop complex RFICs for 4G/5G and WLAN applications.

You will perform transistor-level design, validate circuits with simulations, and collaborate with layout and test teams to ensure performance targets are met. Applicants should have a degree in Electrical Engineering with several years of ASIC/RF design experience and proficiency in Cadence, Virtuoso, and ADS.