Senior RF Front-End Module Architect for Starlink

SpaceX; Palo Alto (CA); Presencial; USD 175.000 - 280.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Stock options

Medical coverage

401(k) plan

Paid vacation

Descripción de la vacante

SpaceX is seeking a Sr. RF Front-End Module Design Engineer to develop compact multi-chip RF front-end modules for the Starlink Mobile network.

You will specify, design, simulate, fabricate, and debug MCMs containing RFICs, filters, and passives, collaborating with RFIC/BAW designers and layout engineers to optimize performance for 5G NR, LTE, and Wi‑Fi. Requires a strong background in RF engineering, multi-chip module design, and production-ready integration.

Formación

• Bachelor's degree in electrical engineering, computer engineering, or computer science.
• 5+ years of RF/Microwave engineering or RFIC experience.
• Experience with RF front-end modules, BAW/SAW filters, and RFIC integration.

Responsabilidades

• Design and develop RF front-end MCMs for 5G NR, LTE, and Wi-Fi.
• Integrate RFICs, power management ICs, BAW/SAW filters, and other passives into compact MCMs.
• Design custom passives printed into module laminates.
• Specify RFIC and BAW filter performances; define pin-to-pin lineups and linearity.
• Work with RFIC designers, BAW filter designers, and package/layout engineers on module floor-planning.
• Perform detailed circuit and EM simulations and co-simulations with sub-components.
• Lab bring-up, characterization, and debugging of module prototypes; drive learnings into improvements.
• Manage laminate and assembly suppliers; develop ATE test plans with OSAT teams.
• Support integration of RF modules into production PCBAs; perform yield analysis and design improvements.

Conocimientos

RF Engineering

RFIC Design

Multichip MCMs

Python / MATLAB

RF Testing Equipment

Educación

Bachelor's degree in Electrical Engineering

Herramientas

ADS

HFSS

AWR

MATLAB

Python

Descripción del empleo

SpaceX is seeking a Sr. RF Front-End Module Design Engineer to develop compact multi-chip RF front-end modules for the Starlink Mobile network.

You will specify, design, simulate, fabricate, and debug MCMs containing RFICs, filters, and passives, collaborating with RFIC/BAW designers and layout engineers to optimize performance for 5G NR, LTE, and Wi‑Fi. Requires a strong background in RF engineering, multi-chip module design, and production-ready integration.