Senior Process Integration Engineer – Embedded Flash Memory

Microchip Technology Inc.; San Jose (CA); On-site; USD 91,000 - 232,000; Full time

Job summary

Microchip Technology Inc. invites applications for a Technical Staff Process Integration Engineer to lead development of next‑generation embedded flash memory technology, driving process setup, silicon validation, and reliability qualification on tight schedules.

The role includes cross‑functional leadership across teams, collaboration with foundries, and exposure to memory solution production. Travel 0%–25% is expected.

Qualifications

• In‑depth knowledge of advanced‑node CMOS process integration and device physics.
• Strong analytical, organizational, and communication skills.
• Experience in non‑volatile memory technology development; flash memory array characterization is a plus.
• Proficiency in TCAD, PDK, circuit design, layout, device/product characterization, reliability, and qualification.
• Ability to work well in fast‑paced, multifunctional, multi‑time‑zone teams.

Responsibilities

• Embedded flash memory technology development, including process integration, design rule scaling, device optimization, failure analysis, and yield enhancement.
• Technical project management: manage cross‑functional and cross‑organizational teams to accomplish process setup, test chip tape‑out, silicon validation, yield demonstration, and reliability qualification on schedule.
• Interface with foundry, IDM, and design house partners.

Skills

CMOS process integration

Device physics

TCAD

PDK

Circuit design

Layout

Reliability qualification

Cross-functional teamwork

Education

Bachelor's degree in Electrical Engineering

Tools

TCAD

PDK

Device characterization tools

Job description

Microchip Technology Inc. invites applications for a Technical Staff Process Integration Engineer to lead development of next‑generation embedded flash memory technology, driving process setup, silicon validation, and reliability qualification on tight schedules.

The role includes cross‑functional leadership across teams, collaboration with foundries, and exposure to memory solution production. Travel 0%–25% is expected.