Senior Process Integration Engineer

Tokyo Electron US; City of Albany (NY); On-site; USD 100,000 - 140,000; Full time

Job summary

An established industry player is seeking a Senior Process Integration Engineer to drive semiconductor technology development. This role involves optimizing manufacturing processes for logic and memory devices, collaborating with various teams to integrate new materials and architectures. You will design and execute experiments, manage projects, and ensure high-quality standards in a cleanroom environment. Join a forward-thinking company that values diversity and innovation, and make a significant impact in the semiconductor industry.

Benefits

Medical insurance

Vision insurance

401(k)

Paid maternity leave

Paid paternity leave

Tuition assistance

Disability insurance

Qualifications

• 5+ years in semiconductor industry engineering required.
• Experience in litho processing and mask installation is desirable.

Responsibilities

• Develop new process flows for logic device manufacturing.
• Support customers in solving integrated process issues.

Skills

Measurement and analysis tool operation

EUV Lithography

Project management

Communication skills

Problem-solving skills

Data analysis

Experiment design (DOE)

Education

Master’s degree in related science/engineering

PhD in related field

Tools

Quartz PCI measurement software

MS Office

Statistical software (Excel, JMP)

Job description

Direct message the job poster from Tokyo Electron US

Talent Acquisition Technical Recruiter at Tokyo Electron US

Senior Process Integration Engineer

As a Sr. Process Integration Engineer for FEOL/MOL in the Advanced Sample Development team for logic and memory devices you will drive semiconductor technology development activities related to pitch scaling, new materials and new device architectures integration.

You will work closely with other groups within TEL to verify and integrate various processes to demonstrate benefits of TEL technologies. You will be responsible for building new processing routes and running experiments across litho, etch, films and wets will be required.

Responsibilities

• Responsible for development of new process flow and integrations to optimize and assist in logic device manufacturing of TEL internal test samples
• Support customers in solving their integrated and process issues through current and future capabilities of TEL equipment.
• Work seamlessly with all of TEL factories and onsite BU(s) to incorporate their product roadmap and capabilities with customers current and future needs through standard and novel integration flows.
• Design experiments, execute and demonstrate proposed solutions on TEL internal vehicle including analysis and statistical analysis.
• Coordinate with each BU to conform to overall TEL business goals.
• Lot management including process split, DOEs, metrology setup and data analysis/evaluation
• Maintain and execute a high degree of quality control techniques to ensure excellence
• Strong data analysis, record keeping and organizational skills required

Preferred & Required Skills

• Measurement and analysis tool operation skills are required including inline CDSEM and cross-sectional SEM.
• EUV Lithography and or immersion 193i experience would be preferred.
• Work self-management, teamwork and collaboration skills are required.
• Experience in project management, planning and scheduling is desirable.
• Individual must have excellent verbal and written communication skills including presentations.
• Knowledge of experiment design (DOE) and techniques for tool and process optimization is required.
• Strong Problem-solving skills required.
• In-depth knowledge and skill for personal computer including peripheral equipment and software are required (MS Windows, MS Office, network, etc.)
• Strong data analysis skills are needed. Experience with Quartz PCI measurement software, Excel, JMP or other statistical software is preferred.

Typical Education and Experience

• Master’s degree required in related science/engineering field, preferably Chemical Engineering, Materials Science/Engineering, Mechanical Engineering, Electrical Engineering, Chemistry, or Physics with minimum 5 years of related work experience in semiconductor industry engineering or PhD with minimum 3 years’ experience.
• Semiconductor unit process experience in the area of litho processing recipe set up (scanner and track) and mask installation is desirable, other unit process experience in etch/ films/CMP also beneficial.
• Semiconductor integration experience is preferred.
• U.S. work authorization is required.

Physical Demands and Work Conditions

This job operates in both an office and a cleanroom setting. This role routinely uses standard office equipment such as computers, phones, photocopiers, and filing cabinets. This is a largely sedentary role; however, some filing is required, which would require the ability to lift files, open filing cabinets and bend or stand as necessary. This position requires the ability to occasionally lift office products and supplies, up to 35 pounds. Candidates must be able to work in a clean room environment, which includes wearing specialized clean room attire (such as gowns, gloves, masks, and hairnets) for extended periods, and lifting/carrying foups. This position also requires 4 to 6 hours per day at a computer screen/keyboard and remaining time spent in the cleanroom or lab. Candidates should be comfortable working in a highly regulated, meticulous setting where adherence to strict cleanliness and safety protocols is essential.

Diversity creates an innovative culture. TEL US is an Equal Employment Opportunity / Affirmative Action employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, national origin, protected veteran status, disability status, sexual orientation, gender identity or expression, marital status, genetic information, or any other characteristic protected by law.

Equal Opportunity Employer/Minorities/Females/Disabled/Veterans

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering and Research

• Industries

  Semiconductor Manufacturing

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Inferred from the description for this job

Medical insurance

Vision insurance

401(k)

Paid maternity leave

Paid paternity leave

Tuition assistance

Disability insurance

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