Senior Process Engineer

Kopin Corporation; Westborough (MA); On-site; USD 130,000 - 150,000; Full time

Job summary

Kopin Corporation in Massachusetts is seeking a Senior Process Engineer to lead the development, optimization, and scale-up of our micro-LED display manufacturing technology. You will apply hands-on experience in die-level bonding, lithography, and metal deposition to drive a robust transition from R&D to high-volume production.

The role emphasizes DOE design, SPC implementation, root-cause analysis, and close collaboration with equipment suppliers to qualify new tools and improve yield.

Qualifications

• U.S. Citizen or permanent resident required due to ITAR
• Bachelor of Science with exceptional hands-on semiconductor experience accepted; MS/PhD preferred
• 8+ years of hands-on semiconductor process engineering experience with emphasis on die-level bonding, advanced packaging, or assembly

Responsibilities

• Lead die-level bonding process development and optimization
• Develop, characterize, and optimize indium bump formation and under bump metal (UBM) deposition
• Design, execute, and analyze DOE to map process windows and improve yield and reliability
• Implement SPC methodologies to monitor process stability and drive continuous improvement
• Collaborate with equipment suppliers for tool qualifications and in-field bonding trials
• Interface with wafer/ chip suppliers to ensure material quality and compatibility
• Document robust process specifications, work instructions, and training materials

Skills

Die-level bonding

Thermo-Compression Bonding

Flip-Chip Attach

Lithography

Metal Deposition

Data analysis

DOE design of experiments

SPC

Root-cause analysis

Communication

Cross-functional collaboration

Education

Bachelor of Science

MS/PhD in Materials Science, Chemical Engineering, Mechanical Engineering, Electrical Engineering, Physics or related field

Tools

JMP

Minitab

Job description

The Senior Process Engineer will lead the development, optimization, and scale-up of our micro-LED display manufacturing technology. Responsibility includes extensive hands-on experience in die-level bonding techniques, with a deep understanding of the full semiconductor process flow, including lithography and metal deposition. This position plays the lead role in both prototype fabrication and transferring technology from R&D to high-volume manufacturing.

JOB DUTIES AND RESPONSIBILITIES:

• Develop, characterize, and optimize indium bump formation processes:
• Vacuum deposition (sputtering/evaporation) of under bump metal (UBM) and Indium
• Photolithography and lift-off patterning
• Bump geometry, pitch scaling, and bump surface quality
• Lead the process development of thermo-compression bonding for Chip-to-chip/die-to-die application:
• Design, execute, and analyze Design of Experiments (DOE) to characterize process windows, identify key control parameters, and improve bond yield, uniformity, and reliability.
• Perform root cause analysis for bonding-related failures (e.g., misalignment, non-contact, cracked die, high resistance) using SEM, FIB, X-ray and electrical testing
• Collaborate closely with equipment suppliers to perform both Indium bumping process and bonding trials at equipment vendor sites (travel required).
• Responsible for new tool qualifications, oversee preventative maintenances.
• Interface with chip and wafer supplier to ensure incoming material quality and compatibility with the bonding process.
• Develop and document robust process specifications, work instructions, and training materials for technicians.
• Implement Statistical Process Control (SPC) methodologies to monitor process stability and drive continuous improvement initiatives.
• Remains current with the latest advancements in advanced packaging, bonding techniques, and mass transfer technologies.

MINIMUM JOB QUALIFICATIONS:

• Kopin is a defense contractor and is subject to International Traffic in Arms Regulations (ITAR). You must be a US Citizen or Permanent Resident (green card holder) to be considered for this position.
• A Bachelor of Science with exceptional demonstrated experience will be considered. M.S. or Ph.D. in Materials Science, Chemical Engineering, Mechanical Engineering, Electrical Engineering, Physics, or a related field, preferred.
• 8+ years of hands-on experience in semiconductor process engineering, with a specific focus on die-level bonding, advanced packaging, or assembly.
• Proven, in-depth experience with one or more of the following is strongly preferred:
• Thermo-Compression Bonding (TCB)
• Flip-Chip Attach process and materials
• Strong experience with bonding metrology and failure analysis techniques (C-SAM, X-ray, SEM/EDX, bond pull/shear testing).
• Strong foundational experience in other key semiconductor unit processes:
• Lithography: Hands-on experience with photoresist processing (coat, expose, develop), overlay registration, and critical dimension control. Knowledge of steppers/scanners is essential.
• Metal Deposition: Practical knowledge of Physical Vapor Deposition (PVD) techniques such as sputtering and evaporation for depositing adhesion layers, diffusion barriers, and seed layers (e.g., Ti, Cu, Al).
• Working Knowledge of silicon wafer dicing and coring processes, experience in wafer-to-chip singulation, yield improving, and minimizing die damages through data-driven process engineering.
• Proficiency in data analysis tools such as JMP, Minitab and experience with SPC and DOE.
• Deep understanding of interface science, solder metallurgy, and intermetallic compound (IMC) formation.
• Exceptional problem-solving skills and a data-driven, analytical approach to root cause investigation.
• Meticulous attention to detail and a relentless focus on yield and quality.
• Strong ability to work collaboratively in a cross-functional team environment.
• Excellent communication skills for effectively reporting findings and recommendations to both technical and management/leadership audiences.
• Self-motivated and capable of managing multiple projects in a fast-paced, startup-like environment.

PREFERRED QUALIFICATIONS

• M.S. or Ph.D. in Materials Science, Chemical Engineering, Mechanical Engineering, Electrical Engineering, Physics, or a related field preferred. A Bachelor of Science with exceptional demonstrated experience will be considered.
• Direct experience in Micro-LED, LED, or photonics fabrication and integration.
• Experience with thin-film transistor (TFT) backplane integration.
• Knowledge of wafer-level packaging processes.
• Experience in a high-volume manufacturing (HVM) environment and bringing processes from NPI to production.
• Familiarity with equipment from key vendors in the bonding and packaging space.

PHYSICAL REQUIREMENTS:

• Work is performed in an office environment and requires the ability to operate standard office equipment. Prolonged periods sitting at a desk and working on a computer. Must have the ability to lift 15 pounds and carry small parcels, packages, and other items, walk short distances, and gown according to clean room protocols as required.

**The approximate salary range for this position is $130,000 to $150,000 annually, plus bonus**