Principal Layout Designer, Next-generation HBM Architecture

1000 Micron Technology, Inc.; Richardson (TX); On-site; USD 85,755 - 168,067; Full time

Benefits offered by this job

Medical, dental, and vision plans

Paid family leave

Robust paid time-off program

Job summary

1000 Micron Technology, Inc. is seeking a Principal Layout Designer for their AI-optimized Architecture team in Richardson, Texas. This role involves driving layout activities for high-performance memory supporting AI workloads, focusing on design excellence across analog and digital domains.

The ideal candidate will have a Bachelor's or Master’s degree in relevant fields and at least 10 years of experience designing DRAM layouts. Strong communication skills and familiarity with Cadence tools are essential, along with a comprehensive benefits package.

Qualifications

• 10+ years of experience in analog and custom layout designs.
• Extensive hands-on layout experience with critical DRAM blocks.
• Solid understanding of layout impacts: speed, capacitance, power, area.

Responsibilities

• Design and develop critical analog, mixed‑signal, and custom digital blocks.
• Drive exploratory layout processes for next‑generation architectures.
• Integrate full chip designs and perform layout verification.

Skills

Layout design

Cadence VLE/VXL

Mentor Graphics Calibre DRC/LVS

Analog layout fundamentals

Communication skills

Education

Bachelor’s or Master’s in Computer Science, Computer Engineering, Electrical Engineering

Tools

Cadence

Mentor Graphics

Job description

Job Overview

As a Principal Layout Designer in Micron Technology’s AI‑optimized Architecture team, you will drive DRAM layout activities for high‑performance memory that supports AI workloads. Your work will span analog, mixed‑signal, and custom digital domains, collaborating with architecture, design, and packaging teams to identify optimizations and ensure feasible design concepts.

Responsibilities

• Design and develop critical analog, mixed‑signal, and custom digital blocks.
• Drive exploratory layout processes for next‑generation architectures, including floor planning, placement, and routing.
• Integrate full chip designs and perform layout verification (LVS, DRC), quality checks, and documentation.
• Collaborate and communicate across domains—signal integrity, architecture, design, and sophisticated packaging—to support successful architecture exploration.

Minimum Qualifications

• Demonstrated ability with a Bachelor’s or Master’s in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience.
• Extensive hands‑on layout experience with critical DRAM blocks and complete designs.
• Experience with Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS.
• Solid understanding of layout impacts: speed, capacitance, power, and area.
• Strong knowledge of analog layout fundamentals—matching, electro‑migration, latch‑up, coupling, crosstalk, IR‑drop, and parasitic effects.

Preferred Qualifications

• 10+ years of experience in analog and custom layout designs.
• Proven layout ability with advanced CMOS processes across technology nodes (e.g., FinFET).
• Excellent communication and interpersonal skills.

Compensation

US base salary range: $62.25 – $122.00 per hour. Additional compensation may include benefits, bonuses, and equity.

Benefits

Micron provides a range of health benefits—including medical, dental, and vision plans—across all locations. Employees also receive income protection programs, paid family leave, a robust paid time‑off program, paid holidays, and a comprehensive benefit guide available at micron.com/careers/benefits.

EEO Statement

Micron is proud to be an equal‑opportunity workplace and an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity, or any other factor protected by applicable federal, state, or local laws.