Principal Layout Designer, Next-generation HBM Architecture

Micron Technology; Folsom (CA); On-site; USD 85,755 - 168,067; Full time

Benefits offered by this job

Medical, dental, and vision plans

Paid time-off program

Paid family leave

Job summary

Micron Technology in Folsom, California is seeking a skilled individual to design and develop critical analog, mixed-signal, and custom digital blocks. You will work on next-generation architectures, integrating full chip designs while performing thorough layout verification.

This position requires a Bachelor's or Master's in a relevant field, with extensive hands-on experience in DRAM layout. The salary range for this full-time position is estimated at $62.25 - $122.00 per hour, complemented by benefits and a robust paid time-off program.

Qualifications

• Demonstrated knowledge in layout design, particularly with critical DRAM blocks.
• Extensive hands-on layout experience.
• Solid understanding of layout impacts such as speed, capacitance, power, and area.

Responsibilities

• Design and develop critical analog and mixed-signal blocks.
• Drive exploratory layout processes for next-generation architectures.
• Integrate full chip designs and perform layout verification.

Skills

Analog layout fundamentals

DRAM block layout

Communication skills

Layout verification

Collaboration across domains

Education

Bachelor's or Master's in Computer Science/Engineering or equivalent

Tools

Cadence VLE/VXL

Mentor Graphics Calibre DRC/LVS

Job description

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Our vision is to transform how the world uses information to enrich life for all.

Responsibilities

• Design and develop critical analog, mixed‑signal, and custom digital blocks.
• Drive exploratory layout process for next‑generation architectures, including floor planning, placement, and routing.
• Integrate full chip designs and perform layout verification (LVS, DRC), quality checks, and documentation.
• Collaborate and communicate across domains, including signal integrity, architecture, design, and sophisticated packaging, to ensure successful architecture exploration.

Minimum Qualifications

• Demonstrated ability with a Bachelor’s or Master’s in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience.
• Extensive hands‑on layout experience with critical DRAM blocks and full designs.
• Experience with Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS.
• Solid understanding of layout impacts: speed, capacitance, power, and area.
• Strong understanding of analog layout fundamentals: matching, electro migration, latch‑up, coupling, crosstalk, IR‑drop, and parasitic effects.

Preferred Qualifications

• 10+ years of experience in analog and custom layout designs.
• Proven layout ability with advanced CMOS processes across technology nodes (e.g., FinFET).
• Excellent communication and interpersonal skills.

US base salary range that Micron Technology estimates it could pay for this full‑time position is: $62.25 - $122.00 an hour.

Additional compensation may include benefits, bonuses and equity.

Micron offers a choice of medical, dental and vision plans in all locations, allows team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that protect income if a person is unable to work due to illness or injury, and paid family leave. Additionally, Micron offers a robust paid time‑off program and paid holidays.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.