Senior Principal Engineer - Emulation & Prototyping

GSME; San Jose (CA); On-site; USD 230,000 - 320,000; Full time

Job summary

GSME is seeking an experienced Senior Principal Engineer to drive pre-silicon validation across IP blocks to multi-billion-gate SoCs, leveraging emulation and FPGA prototyping platforms.

You will own platform components, mentor engineers, and ensure smooth RTL-to-silicon transitions for internal and customer projects, while collaborating with partners to advance methodologies and tool usage.

Qualifications

• Masters degree in electrical/computer engineering with 15+ years industry experience.
• Expert in hardware emulation and FPGA prototyping with proven success on IP blocks to large SoCs; experience working with customers/partners.
• Strong experience with two or more leading commercial emulation/prototyping platforms from Cadence, Siemens, and/or Synopsys.
• Solid experience with multi-FPGA partitioning, synthesis, place-and-route, and timing closure.
• Strong proficiency in Verilog/SystemVerilog, RTL synthesis tools (Synopsys DC, Cadence Genus), static timing analysis, and RTL debug.
• Proven track record with bring-up and debug of high-speed interfaces: PCIe Gen5/6, CXL, DDR5, HBM3/3E, Ethernet 400/800G, UCIe.
• Solid scripting and automation skills (Python, Perl, Tcl, Bash, Makefile/CMake) for flow development and testing.
• Demonstrated ability to mentor and guide other engineers on technical work.

Responsibilities

• Design, build, and optimize system level emulation and FPGA prototyping platforms capable of handling designs from IP modules to large multi-billion-gate SoCs.
• Own bring-up, debug, and optimization of system level design models onto commercial emulation systems and FPGA prototyping systems.
• Develop and implement methodologies for IP-level, SoC-level, and System-level prototyping flows, including: High-speed interface bring-up in emulation or prototyping environment; Emulation/FPGA specific modifications; Drive adoption of advanced system-level pre-silicon validation use cases with emulation and prototyping including early software/firmware development and co-verification, power estimation and optimization, performance characterization, etc.
• Establish efficient flows for design iterations --- from IP validation to full-chip SoC tape-out readiness.
• Perform complex debug of hardware/software issues using advanced tools (Verdi, DVE, Vivado Hardware Manager, SignalTap, transaction viewers, JTAG/trace debuggers).
• Collaborate with various customer RTL design/verification/software teams to resolve design issues and performance challenges.
• Mentor mid-level and senior engineers on technical topics and best practices; contribute to team technical direction.
• Evaluate new tools, platforms, and technologies to improve platform capabilities and turnaround time.
• Support silicon bring-up by assisting with transition of emulation/prototyping environments to lab hardware and initial silicon validation.
• Participate in vendor technical engagements to address platform needs and optimize tool usage.

Skills

Mentorship

Technical leadership

RTL debugging

Education

Master's degree in electrical/computer engineering

Tools

Cadence

Siemens

Synopsys

Verdi

DVE

Vivado

Job description

GSME is seeking an experienced Senior Principal Engineer to contribute to our world-class emulation and FPGA prototyping organization. This strategic technical individual contributor leadership role will drive pre-silicon validation across a wide range of our designs --- from IP blocks (controllers, accelerators, interfaces) to multi-billion-gate SoCs targeting AI/ML, automotive, data-center, networking, and high-performance computing markets. As a senior technical expert in emulation and/or FPGA prototyping, you will develop and deploy advanced methodologies, own major platform components, ensure seamless transition from RTL to working silicon for internal and customer projects, and be the mentor and coach for other team members.

Key Responsibilities

• Design, build, and optimize system level emulation and FPGA prototyping platforms capable of handling designs from IP modules to large multi-billion-gate SoCs.
• Own bring-up, debug, and optimization of system level design models onto commercial emulation systems and FPGA prototyping systems.
• Develop and implement methodologies for IP-level, SoC-level, and System-level prototyping flows, including:
  • High-speed interface bring-up in emulation or prototyping environment
  • Emulation/FPGA specific modifications
  • Drive adoption of advanced system-level pre-silicon validation use cases with emulation and prototyping including early software/firmware development and co-verification, power estimation and optimization, performance characterization, etc.
• Establish efficient flows for design iterations --- from IP validation to full-chip SoC tape-out readiness.
• Perform complex debug of hardware/software issues using advanced tools (Verdi, DVE, Vivado Hardware Manager, SignalTap, transaction viewers, JTAG/trace debuggers).
• Collaborate with various customer RTL design/verification/software teams to resolve design issues and performance challenges.
• Mentor mid-level and senior engineers on technical topics and best practices; contribute to team technical direction.
• Evaluate new tools, platforms, and technologies to improve platform capabilities and turnaround time.
• Support silicon bring-up by assisting with transition of emulation/prototyping environments to lab hardware and initial silicon validation.
• Participate in vendor technical engagements to address platform needs and optimize tool usage.

Qualifications

Required Qualifications

• Masters degree in electrical/computer engineering with 15+ years industry experience.
• Recognized expert in multiple domains with hands-on industry experience in hardware emulation and FPGA prototyping, with proven success on designs ranging from IP blocks to large SoCs. Proven ability to work with customers/partners is a big plus.
• Strong experience with two or more leading commercial emulation/prototyping platforms from Cadence, Siemens, and/or Synopsys.
• Solid experience with multi-FPGA partitioning, synthesis, place-and-route, and timing closure.
• Strong proficiency in Verilog/SystemVerilog, RTL synthesis tools (Synopsys DC, Cadence Genus), static timing analysis, and RTL debug.
• Proven track record with bring-up and debug of one or more high-speed interfaces: like PCIe Gen5/6, CXL, DDR5, HBM3/3E, Ethernet 400/800G, UCIe.
• Solid scripting and automation skills (Python, Perl, Tcl, Bash, Makefile/CMake) for flow development and testing.
• Demonstrated ability to mentor and guide other engineers on technical work.

Preferred Qualifications

• Experience with power-aware emulation, transaction-level modeling (TLM), virtual platforms (SystemC TLM-2.0), or hybrid emulation/virtual platform flows.
• Familiarity with formal verification, UVM, coverage-driven verification, or low-power design methodologies.
• Hands-on experience with x86/ARM/RISC-V subsystems, BIOS/firmware bring-up, and OS-level software validation on prototypes.
• Prior work on AI/ML accelerators, automotive SoCs (ADAS, zonal), data-center chips, or networking ASICs.
• Patents, publications, or contributions to industry standards in emulation/prototyping.