Senior Principal Design Engineer - STA/Timing

Ampere; Santa Clara (CA); On-site; USD 237,000 - 356,000; Full time

Benefits offered by this job

Health insurance

401K plan

Unlimited flextime

Job summary

Ampere Computing is seeking a Senior Principal Design Engineer specializing in Static Timing Analysis (STA) to drive timing closure for advanced CPU/SoC designs. This highly visible leadership role will define timing strategies, solve timing challenges, and influence design methodologies across projects.

Ideal candidate combines deep STA, physical design, timing analysis, and semiconductor development flows with strong leadership and communication skills, able to operate strategically and

Qualifications

• Extensive hands-on STA and timing-closure experience for ASIC/CPU/SoC designs.
• Strong leadership, mentoring, and cross-functional collaboration skills.
• Excellent written and verbal communication for senior audiences.

Responsibilities

• Own and lead STA and timing-closure activities across CPU, SoC, and IP designs.
• Define timing constraints, analysis methodologies, signoff criteria, and guidelines.
• -drive timing closure from RTL through tapeout and signoff.
• Analyze setup/hold, recovery, clock-domain, and variation-related timing issues.
• Mentor engineers and officers timing methodology across programs.

Skills

STA expertise

Timing closure

Digital design

Scripting

Leadership

Education

Electrical or Computer Engineering degree

Tools

Synopsys PrimeTime

Cadence Innovus

Design Compiler

Fusion Compiler

ICC2

Job description

Invent the future with us. Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AIcompute. As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications. Join us at Ampere and work alongside a passionate and growing team.

About The Role

Ampere Computing is seeking a Senior Principal Design Engineer specializing in Static Timing Analysis (STA) and timing methodology to drive timing closure for advanced CPU and SoC designs. This highly visible technical leadership role will define timing strategies, solve complex timing challenges, and influence design, implementation, and verification methodologies across multiple projects. The ideal candidate combines deep expertise in STA, physical design, timing analysis, and semiconductor development flows with strong leadership and communication skills. This role requires the ability to operate at both strategic and hands-on technical levels, from methodology definition through signoff and silicon readiness.

What You Will Achieve

• Own and lead STA and timing-closure activities across complex CPU, SoC, and IP designs.
• Define timing constraints, analysis methodologies, signoff criteria, and implementation guidelines.
• Drive timing closure from RTL through synthesis, place and route, signoff, and tapeout.
• Analyze and resolve setup, hold, recovery, removal, pulse-width, clock-domain, and variation-related timing issues.
• Develop and maintain timing constraints, including clocks, generated clocks, false paths, multicycle paths, asynchronous paths, and interface timing.
• Lead analysis across PVT corners, RC corners, operating modes, voltage domains, and advanced variation models.
• Partner closely with RTL, microarchitecture, logic design, physical design, clocking, power, DFT, CAD, and silicon validation teams.
• Establish and improve timing methodologies, automation, dashboards, and quality checks.
• Identify timing risks early and provide architectural or implementation recommendations to mitigate them.
• Evaluate and deploy timing-analysis tools, flows, scripts, and signoff practices.
• Mentor senior and junior engineers and serve as a technical authority for STA and timing closure.
• Present timing status, risks, tradeoffs, and recommendations to engineering leadership.
• Contribute to cross-functional planning, project estimation, and execution for future CPU and SoC programs.

About You

As a Senior Principal Engineer, you will be expected to:

• Set technical direction for STA and timing closure across programs.
• Make high-impact decisions in ambiguous and time-sensitive situations.
• Establish scalable processes and reusable methodologies.
• Raise the technical capability of the broader organization through mentoring and knowledge sharing.
• Extensive hands-on experience with STA and timing closure for complex ASIC, CPU, SoC, or high-performance digital designs.
• Strong understanding of:
  • Digital logic and synchronous design principles
  • Clock-tree design and clock-domain interactions
  • OCV, AOCV, POCV, LVF, derates, and variation-aware timing
  • Signal integrity, crosstalk, noise, and advanced-node effects
  • Multi-voltage and power-intent-aware timing analysis
  • Timing constraints and exception validation
  • MCMM analysis and signoff requirements
  • ECO implementation and timing optimization
• Experience with industry-standard tools such as Synopsys PrimeTime, PrimeClosure, Design Compiler, Fusion Compiler, ICC2, Cadence Tempus, Innovus, or equivalent.
• Strong scripting and automation skills using Tcl, Python, Perl, or similar languages.
• Demonstrated ability to lead complex technical efforts across multiple engineering organizations.
• Excellent written, verbal, and cross-functional communication skills.
• Experience with high-performance CPU or server-class SoC timing closure.
• Experience at advanced process nodes and with complex hierarchical or chiplet-based designs.
• Familiarity with Liberty, SDC, SPEF, parasitic extraction, timing models, and library characterization.
• Experience with formal constraint validation, CDC/RDC analysis, and timing signoff correlation.
• Knowledge of low-power design methodologies, UPF, voltage islands, level shifters, isolation, and retention structures.
• Experience developing timing methodologies for large, distributed design teams.
• Track record of influencing architecture or RTL to achieve performance, power, and area goals.
• Experience with signoff automation, data analytics, and timing-quality metrics.
• Electrical or Computer Engineering - Bachelor’s degree & 12 years of related experience in semiconductor design, physical design, timing analysis or related areas; or master's degree & 8 years; or PhD & 5 years

What We’ll Offer

At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, cash long-term incentive, and comprehensive benefits. The full base pay range for this role is between $237,000 and $356,000. Our benefits include health, wellness, and financial programs that support employees through every stage of life.

Benefit Highlights Include

• Premium medical insurance, dental insurance, vision insurance, as well as income protection and a 401K retirement plan, so that you can feel secure in your health and financial future.
• Unlimited Flextime and 10+ paid holidays so that you can embrace a healthy work-life balance.
• A variety of healthy snacks, energizing espresso, and refreshing drinks to keep you fueled and focused throughout the day.

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.