Senior Principal Design for Test Engineer

Ampere; Santa Clara (CA); On-site; USD 237,000 - 356,000; Full time

Benefits offered by this job

Health insurance

Dental insurance

Vision insurance

401K retirement plan

Unlimited flextime

Paid holidays

Job summary

Ampere is seeking a highly skilled engineer to design, implement, and verify DFT features for next-generation server-class processors. You will collaborate with global teams to deliver robust test solutions and drive post-silicon bring-up activities.

The role requires strong Verilog HDL, MBIST/EDT/SSN expertise, and hands-on experience with ATE data, as well as proficiency in major EDA tool flows from Mentor, Cadence, and Synopsys.

Qualifications

• Experience designing and verifying DFT features for high-end processors.
• Hands-on MBIST, boundary scan, JTAG/IJTAG in advanced nodes.
• Proficient in Verilog HDL and debugging tools.
• Experience with ATE patterns and post-silicon bring-up.
• Ability to work with Mentor, Cadence, Synopsys tool flows.

Responsibilities

• Collaborate with global teams to design, implement and verify DFT features.
• Develop ATE patterns and support post-silicon bring-up and debugging.
• Perform RTL/gate-level simulations and waveform debugging.
• Lead test plans and coverage analysis for DFT and MBIST.

Skills

Verilog HDL

MBIST

DFT

Test planning

Scripting (Perl/Tcl)

Python

JTAG/IJTAG

Education

Electrical or Computer Engineering degree

Bachelor’s/Master’s/PhD with years experience

Tools

Siemens Tessent

Synopsys SMS/SHS

Mentor Graphics

Cadence

Job description

Invent the future with us.

Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute.

Description

As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications.

Join us at Ampere and work alongside a passionate and growing team.

About The Role

The ideal candidate will work with multi-functional global teams to design, implement and verify Boundary Scan, ATPG (Stuck-AT/AT-Speed) SCAN, MBIST, IOBIST and JTAG/IJTAG DFT features on our next generation highly complex server class processor products. Will work in close collaboration with test engineering team to deliver ATE patterns and post silicon bring-up and debug.

What You'll Achieve

• DFT features like EDT, SSN, shared bus based MBIST insertion, ijtag, simulation and debug on RTL and gates netlist for automotive applications.
• Boundary Scan insertion, simulation and verification.
• Scan insertion, Scan compression, Stuck-At, At-Speed test and coverage analysis
• Scan ATPG pattern generation, simulation and debug on RTL and gatesnetlist
• Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification (Mentor, Cadence, Synopsys)
• STA DFT Test mode timing constraint development and analysis
• In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools
• ATE silicon debug and utilize scripting with perl/Tcl for efficient handling of ATE data

About You

• Expert with methods and techniques to design, implement and verify regular and shared bus based Memory BIST on repairable and non-repairable memories using Electrical fuses.
• Expert knowledge and practical work experience partnering with designers to implement highly customized and tools-driven MBIST solutions.
• Solid understanding of MBIST algorithms needed for 5nm and lower technology nodes and ability to code new algorithms, operation sets supporting tool driven solutions for functional safety applications.
• Experience in implementing EDT, SSN, IST, boundary scan, jtag/ijtag features.
• Work independently to generate test plans, run simulations and debug failures on RTL and Gate Level.
• Hands on experience in the usage of industry standard tools, like Siemens Tessent Shell flow, or Synopsys SMS/SHS flow
• Experience in Multimedia subsystems DFT (Image, display, video etc.)
• Expert understanding tradeoffs to optimize coverage and test time reduction with the ability to foresee physical implementation and timing challenges during early development.
• Experience in working with physical design teams to support STA constraints, reviewing timing reports.
• Expert in using silicon debug/diagnosis tools to root cause silicon bringup and production test issue.
• Experience in setting up and running Scan DRC flows in RTL.
• Experience with industry standard simulation tools, including Verilog, and scripting languages like Perl, Python, Shell or Tcl.
• Experience in revision control systems like GIT, perforce etc.
• Needs in depth experience in stuck at, transition delay, path delay, etc.coverage loss analysis and identifying solutions to improve test coverage
• Experience in leading the effort to derive cell aware fault models and develop necessary flows to generate ATPG and to support silicon debug.
• Good knowledge of functional safety, clock domain crossing analysis, logic synthesis and scan insertion
• Electrical or Computer Engineering - Bachelor’s degree &12 years of related experience; or Master's degree & 8 years; or PhD & 5 years

What We’ll Offer

At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, cash long-term incentive, and comprehensive benefits. The full base pay range for this role is between $237,000 and $356,000.

Our benefits include health, wellness, and financial programs that support employees through every stage of life.

Benefit Highlights Include

• Premium medical insurance, dental insurance, vision insurance, as well as income protection and a 401K retirement plan, so that you can feel secure in your health and financial future.
• Unlimited Flextime and 10+ paid holidays so that you can embrace a healthy work-life balance.
• A variety of healthy snacks, energizing espresso, and refreshing drinks to keep you fueled and focused throughout the day.

And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are excited to share more about our career opportunities with you through the interview process.

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed,

Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds.

All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.