Principal Analog Design Engineer

Qorvo, Inc.; Town of Texas (WI); Hybrid; USD 170,300 - 221,500; Full time

Job summary

Qorvo, Inc. is seeking an experienced Principal Analog Design Engineer in a hybrid role based at Richardson, TX or San Jose, CA.

You will lead design and validation of high-performance analog power management ICs, collaborating with global teams to achieve top-tier efficiency and reliability. The role requires 12+ years in semiconductor analog/mixed-signal IC design, DC-DC power converter knowledge, and strong communication with stakeholders.

Qualifications

• Bachelor’s Degree in Electrical Engineering required.
• 12+ years in semiconductor engineering.
• 8+ years in analog/mixed-signal IC design with DC-DC power converters.
• Strong ability to communicate technical concepts to diverse stakeholders.
• Experience with EDA tools such as EMIR and parasitic extraction flows.
• Production release experience of PMICs.

Responsibilities

• Lead the design and development of high-performance analog power management ICs, ensuring best-in-class efficiency and reliability.
• Collaborate with system engineers to define product architecture and specifications.
• Select and implement optimal circuit topologies, ensuring robustness, yield, and manufacturability.
• Conduct transistor-level design, simulation, and validation to meet specifications.
• Work with layout engineers to optimize floor planning and silicon performance.
• Engage with global design teams to align on development strategies.
• Partner with test/characterization teams to define validation methods and optimize production tests.
• Drive technical reviews and document design decisions and trade-offs.

Skills

Technical communication

Education

Bachelor’s Degree in Electrical Engineering

Masters or PhD in Electrical Engineering

Tools

EMIR

Capacitive coupling tools

Parasitic extraction tools

Floating nodes analysis

Cadence Virtuoso

Simplis

ADS

Job description

Principal Analog Design Engineer

Experience Level: Professional

Job Type: Regular

Location: Richardson, TX, US; San Jose, CA, US

We are seeking a highly skilled Analog Power Design Engineer to develop next-generation, high-performance power management solutions. In this role, you will drive architecture, design, and validation of industry-leading analog power ICs, collaborating closely with cross-functional global teams to deliver world-class products that set new benchmarks in efficiency, reliability, and performance.

This is a hybrid position where the expectation is to be onsite multiple days a week at either our Richardson TX or San Jose CA office.

Responsibilities:

• Lead the design and development of high-performance analog power management ICs, ensuring best-in-class efficiency, power density, and reliability.
• Collaborate with system engineers to define product architecture and specifications, balancing performance, power, and cost requirements.
• Select and implement optimal circuit topologies, ensuring robustness, yield, and manufacturability.
• Conduct transistor-level design, simulation, and validation to meet functional and performance specifications.
• Work closely with layout engineers to optimize floor planning, parasitic, and overall silicon performance.
• Engage with global design teams, including colleagues in Asia, to align on development strategies and execution plans.
• Partner with test and characterization engineers to define validation methodologies, troubleshoot design issues, and optimize production test strategies.
• Drive technical reviews and documentation, presenting design decisions, analysis, and trade-offs to internal stakeholders.

Required Qualifications:

• A minimum of a Bachelor’s Degree in Electrical Engineering.
• 12+ years of engineering experience (or an equivalent amount of education and experience) working in the semiconductor industry.
• 8+ years of experience (or an equivalent amount of education and experience) in analog and mixed-signal IC design, with DC‑DC power converter architectures and control methodologies such as voltage mode control and current mode control.
• Ability to communicate highly technical concepts effectively to both technical and non-technical stakeholders.
• Experience working in Electronic Design Automation (EDA) tools such as EMIR, capacitive coupling tools and flows, parasitic extraction tools, floating nodes, etc.
• Experience with production release of power management ICs.

Preferred Qualifications:

• Masters or PhD in Electrical Engineering.
• Experience with Cadence Virtuoso, Simplis, and ADS.
• Hands‑on lab experience supporting high‑frequency switching power supplies in the semiconductor power management industry.

Competitive base salary commensurate with experience: $170,300 – $221,500, relevant for the California Bay Area (subject to change dependent on physical location).

Posted salary ranges are made in good faith. Qorvo reserves the right to adjust ranges depending on the experience/qualification of the selected candidate as well as external competitiveness and internal comparability.

Base compensation is one element of Total Rewards offered at Qorvo. More information on the Total Rewards package can be shared upon request.

We are an Equal Employment Opportunity (EEO) employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex (as defined by law), national origin, age, military or veteran status, genetic information, or disability.