Senior Analog Power IC Designer — Hybrid

Qorvo, Inc.; Richardson (TX); Hybrid; USD 170,000 - 222,000; Full time

Job summary

Qorvo, Inc. is seeking a Principal Analog Design Engineer to lead the development of high‑performance analog power management ICs. The role is hybrid, onsite several days a week at Richardson, TX or San Jose, CA, with global collaboration across design teams.

Responsibilities include architecture definition, transistor‑level design, layout optimization, and production test strategy. A BSEE is required with 12+ years in analog/mixed‑signal IC design; MS/PhD preferred.

Qualifications

• Bachelor's degree in Electrical Engineering required.
• 12+ years in semiconductor engineering; 8+ years in analog/mixed-signal IC design with DC-DC power converter architectures.
• Ability to communicate complex concepts to technical and non-technical stakeholders.

Responsibilities

• Lead design and development of high-performance analog power management ICs for efficiency and reliability.
• Collaborate with system engineers to define architecture and specifications balancing performance, power and cost.
• Select and implement optimal circuit topologies ensuring robustness and manufacturability.
• Conduct transistor-level design, simulation, and validation to meet specs.
• Work with layout engineers to optimize floor planning and parasitics.
• Coordinate with global design teams to align development strategies.
• Partner with test/characterization teams to define validation methodologies and optimize production tests.
• Drive technical reviews and present trade-offs to stakeholders.

Skills

Analog IC design

Mixed-signal IC design

DC-DC converters

Voltage mode control

Current mode control

EDA tools

Parasitic extraction

Education

Bachelor's degree in Electrical Engineering

Masters or PhD (preferred)

Tools

Cadence Virtuoso

Simplis

ADS

Job description

Qorvo, Inc. is seeking a Principal Analog Design Engineer to lead the development of high‑performance analog power management ICs. The role is hybrid, onsite several days a week at Richardson, TX or San Jose, CA, with global collaboration across design teams.

Responsibilities include architecture definition, transistor‑level design, layout optimization, and production test strategy. A BSEE is required with 12+ years in analog/mixed‑signal IC design; MS/PhD preferred.