Senior Power Integrity Engineer - LPU Packaging

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 196,000 - 310,500; Full time

Job summary

NVIDIA Gruppe in Santa Clara, California, is seeking a Power Integrity Engineer with over 12 years of experience. You will define power delivery practices, collaborate with design teams, and drive system-level designs to ensure optimal performance for GPUs and similar high-power designs.

This role involves hands-on work with advanced packages and requires a strong background in power integrity for high-current applications. Competitive compensation includes a salary range of USD196,000–310,500 based on experience.

Qualifications

• 12+ years of relevant work experience in Power Integrity.
• Proven ownership of chip-package-board PDN design.
• Hands-on experience with FCBGA, 25D/3D integration.

Responsibilities

• Define power delivery design and optimization practices.
• Drive system-level PI design across teams.
• Perform PI extraction and simulation for advanced packages.

Skills

Power integrity expertise

High-current, low-voltage design

Strong communication skills

Education

MS or PhD in Electrical Engineering

Tools

PowerSI

Sigrity

SPICE

Job description

What you’ll be doing

• Define best‑in‑class power delivery design and optimization practices from die/package through board, tray, and rack levels for the full product development cycle
• Own the PI specification and methodology for assigned products, defining PDN targets including impedance, droop, noise, and transient response for GPU, HBM, and high‑speed SerDes
• Architect package‑level PDNs by collaborating with design teams on bump/ball maps, via structures, and decoupling strategies for FCBGA and 25D/3D integrations
• Drive system‑level PI design, including board‑level PDN planning, decap placement, and VRM interfaces while co‑optimizing with SI, thermal, and mechanical teams
• Perform PI extraction and simulation for advanced packages and develop integrated chip–package–board co‑simulation flows using industry‑standard tools
• Generate and deploy reusable PI models, such as SPICE, S‑parameter, and IBIS‑AMI, for use by internal and external partners
• Define and execute comprehensive lab validation plans to correlate measured impedance, noise, and droop against simulation data and specifications
• Debug complex system‑level issues including rail noise, jitter‑induced errors, resets, and margin loss during hardware testing and validation

What we need to see

• MS or PhD in Electrical Engineering or a related field, or equivalent experience
• 12+ years of relevant work experience in Power Integrity
• A strong background in power integrity for high‑current, low‑voltage rails within large GPUs, ASICs, or CPUs
• Proven ownership of the chip‑package‑board PDN design and sign‑off process
• Hands‑on experience with FCBGA, 25D/3D integration, HBM, or similar high‑power, high‑pin‑count packages
• Direct experience in the co‑design of bump/ball maps, power/ground planes, and decoupling capacitor networks
• Proficiency with frequency‑domain PDN impedance analysis and time‑domain transient/droop simulation tools (e.g., PowerSI, PowerDC, Sigrity, RedHawk, Totem, HFSS, SIwave, ADS, or SPICE)
• A deep understanding of board‑level PDN design, including stack‑up definition, plane partitioning, and VRM placement on high‑layer‑count accelerator boards
• Experience in executing lab measurements using VNAs, oscilloscopes, and PDN analyzers to correlate measured noise and droop to original specifications

Ways to stand out from the crowd

• Demonstrated leadership of end‑to‑end PI for a major GPU, CPU, or ASIC program from initial concept through mass production
• Experience with data center or cloud hardware, specifically regarding rack‑level power distribution and how PI choices impact performance headroom
• Background in co‑designing SI and PI for high‑speed interfaces like PCIe, NVLink, CXL, or Ethernet SerDes to mitigate jitter and noise coupling
• Strong communication skills with the ability to clearly explain complex PDN trade‑offs and risks to both technical teams and program stakeholders

Compensation and Benefits

Base salary ranges are USD196,000–310,500 for Level5 and USD232,000–368,000 for Level6, with additional equity and benefits. The offer will be determined by location, experience, and comparable positions.

Equal Opportunity Employment

NVIDIA is committed to fostering a diverse work environment and is an equal‑opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.