Senior Power Integrity Engineer for AI Server Platforms

Majestic Labs ai; Los Altos (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Majestic Labs is seeking a Senior Power Engineer to lead board- and rack-level power delivery for next-gen AI servers. You will define voltage conversion strategies, PDN topology, and decoupling schemes to maximize efficiency and thermal performance while ensuring OCP/Open Rack compatibility.

You will collaborate across silicon, mechanical, thermal, and systems teams, develop test plans, and drive design tradeoffs to ensure robust, scalable power for complex platforms.

Qualifications

• BS/MS in Electrical Engineering or related field.
• 10+ years in high-power delivery design for SoCs.
• Deep expertise in PDN and impedance control for high-current systems.
• Proficiency with SPICE and PDN simulation tools; hands-on measurement experience.
• Strong cross-functional collaboration and communication skills.

Responsibilities

• Architect board-, server-, and rack-level power delivery systems for high-power subsystems.
• Define PDN topology with VRMs, POLs, and high-current interfaces.
• Select components and create derating, margin, and reliability guidelines.
• Lead decoupling capacitor strategy across package/PCB to meet impedance goals.
• Drive power integrity analyses and validate designs via models and lab tests.
• Collaborate with mechanical/thermal teams to meet cooling and routing constraints.
• Co-design vertical PDN paths with silicon and package teams; advise silicon design.
• Develop PDN test plans for validation and bring-up.
• Provide root-cause analysis and corrective actions for power issues.

Skills

High-power design

Power integrity

PDN modeling

VRM design

Transient response optimization

Cross-functional collaboration

Education

Bachelor's/Master's in Electrical Engineering

Tools

SPICE

Keysight

Cadence Sigrity/Clarity

Ansys SIwave

Oscilloscopes

VNAs

Job description

Majestic Labs is seeking a Senior Power Engineer to lead board- and rack-level power delivery for next-gen AI servers. You will define voltage conversion strategies, PDN topology, and decoupling schemes to maximize efficiency and thermal performance while ensuring OCP/Open Rack compatibility.

You will collaborate across silicon, mechanical, thermal, and systems teams, develop test plans, and drive design tradeoffs to ensure robust, scalable power for complex platforms.