Senior Power Integrity Co-Design Engineer - Hybrid

NVIDIA; United States; Hybrid; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits package

Hybrid work

Job summary

NVIDIA is seeking a Senior Power Integrity Co-Design Engineer to architect and deliver di/dt mitigation across silicon, package, board, and platform. You will translate product noise targets into shipped specs and feed silicon findings back into the next generation.

We value strong systems thinking and the ability to operate in ambiguity, with a focus on AI-driven optimization and rigorous engineering judgement. Hybrid work and equity are offered.

Qualifications

• BS/MS/PhD in EE, CE, or related field, or equivalent experience.
• 5+ years in silicon power integrity, voltage noise, or PDN.
• Hands-on silicon bringup, characterization, and correlation.
• Experience with di/dt, droop, and PDN design across die/package/board.

Responsibilities

• Architect voltage-noise mitigation across silicon, package, board, and platform.
• Define product-level voltage-noise targets and drive closure to shipment.
• Develop Sim-to-Si correlation methodology for noise analysis.
• Lead show-stopper noise bugs during bringup and sign-off.
• Collaborate across multiple teams to optimize codesign tradeoffs.

Skills

Power integrity

di/dt analysis

PDN design

Silicon experience

bench test experience

Sim-to-Si correlation

systems thinking

Education

BS/MS/PhD in EE/CE or related

Tools

Oscilloscope

Probes

DAQ

Simulation tools

Job description

NVIDIA is seeking a Senior Power Integrity Co-Design Engineer to architect and deliver di/dt mitigation across silicon, package, board, and platform. You will translate product noise targets into shipped specs and feed silicon findings back into the next generation.

We value strong systems thinking and the ability to operate in ambiguity, with a focus on AI-driven optimization and rigorous engineering judgement. Hybrid work and equity are offered.