Senior PMIC Digital Architect & RTL Lead

NXP Semiconductors; San Jose (CA); On-site; USD 170,000 - 210,000; Full time

Benefits offered by this job

Career development opportunities

Job summary

NXP Semiconductors is hiring a Senior Digital Design Engineer in San Jose, CA to lead digital architecture and implementation for PMICs used in automotive and industrial applications. You will drive RTL development, integration, silicon bring-up, and production release, collaborating across multiple teams.

The role requires a strong background in Verilog/SystemVerilog, RTL design, UVM-based verification, and low-power techniques, with 10+ years in digital IC design and a MS degree in a related

Qualifications

• MS in Electrical Engineering, Computer Engineering, or a related field required.
• Minimum 10 years of experience in digital IC design and development, including leadership and architecture responsibilities.
• Strong understanding of digital design fundamentals, finite state machines, clock-domain crossing, reset architecture, and low-power techniques.
• Expertise in RTL design using Verilog/SystemVerilog for complex digital/mixed-signal ICs.
• Experience with synthesis, static timing analysis, formal verification, and DFT/physical implementation flows.
• Knowledge of modern verification methodologies (UVM, assertions, formal verification, coverage-driven verification).
• Experience developing digital controllers for PMICs or automotive/industrial applications is highly desirable.
• Proficiency with Cadence, Synopsys, and Siemens EDA tools.
• Strong analytical and communication skills for cross-functional leadership.

Responsibilities

• Review requirements, IP architecture, and implementation plans for automotive/industrial PMIC applications.
• Define and implement digital architectures for PMICs, aligning with system requirements.
• Lead digital design from architecture to RTL, timing closure, and production release.
• Design digital control, monitoring, telemetry, diagnostics, configuration, protection, and fault management functions for PMICs.
• Develop RTL, microarchitecture, and design specs using Verilog/SystemVerilog and standard design tools.
• Drive verification strategy including test plans, simulation, formal verification, and coverage analysis.
• Deliver complete IP solutions with RTL, verification collateral, and traceability.
• Track milestones, coverage, defects, and compliance; support silicon bring-up and ramp.

Skills

RTL design

Verilog/SystemVerilog

UVM

Formal verification

Synthesis

Clock-domain crossing

Low-power design

Digital controllers

Power Management ICs (PMICs)

Education

MS in Electrical Engineering or Computer Engineering

Tools

Cadence

Synopsys

Siemens EDA

Job description

NXP Semiconductors is hiring a Senior Digital Design Engineer in San Jose, CA to lead digital architecture and implementation for PMICs used in automotive and industrial applications. You will drive RTL development, integration, silicon bring-up, and production release, collaborating across multiple teams.

The role requires a strong background in Verilog/SystemVerilog, RTL design, UVM-based verification, and low-power techniques, with 10+ years in digital IC design and a MS degree in a related