Lead Analog PMIC Architect for Auto & Industrial Systems

NXP Semiconductors; Chandler (AZ); On-site; USD 150,000 - 230,000; Full time

Job summary

NXP Semiconductors in Chandler, AZ, seeks a seasoned PMIC architect and analog designer to lead the development of high-performance PMICs for automotive and industrial applications. You will define architectures, drive architecture definition, and own design, verification, and validation through production.

Responsibilities include leading DC-DC converter circuitry, error amplifiers, references, protection schemes, and gate drivers, while collaborating with digital and validation teams to ensure

Qualifications

• MSEE required.
• Minimum 10 years in mixed-signal IC development, with >5 years in architecture/leadership.
• Experience with power management designs is highly desirable.
• Familiar with IC electronics physics and analog circuit design.
• Strong English communication and cross-functional collaboration.

Responsibilities

• Lead analog and mixed-signal design for high-performance PMICs in automotive/industrial domains.
• Define IC architecture and drive design, verification, and validation from concept to production.
• Collaborate with digital, system, validation and application teams to deliver scalable PMIC solutions.
• Align targets with customers and product definers and ensure compliance with safety/reliability standards.

Skills

DC-DC architecture

Analog design leadership

Mixed-signal IC development

Cadence Virtuoso/Spectre

English communication

Education

MSEE

Tools

Cadence tools (Virtuoso, Spectre)

Job description

NXP Semiconductors in Chandler, AZ, seeks a seasoned PMIC architect and analog designer to lead the development of high-performance PMICs for automotive and industrial applications. You will define architectures, drive architecture definition, and own design, verification, and validation through production.

Responsibilities include leading DC-DC converter circuitry, error amplifiers, references, protection schemes, and gate drivers, while collaborating with digital and validation teams to ensure