Senior PLL IC Design Engineer for Space-Grade CMOS

Blue Origin LLC; California (MO); Hybrid; USD 230,000 - 323,000; Full time

Benefits offered by this job

Relocation provided

Travel up to 10% of the time

Interviews will include a technical an

Interviews will include a technical a

Job summary

Blue Origin seeks an IC Design Engineer to advance PLLs and clocking systems in cutting-edge CMOS processes. You will own system architecture, optimize phase noise and power, and collaborate with RF and SOC teams to meet stringent space-grade requirements.

You will mentor juniors, drive tape-out readiness, and contribute to robust analog/RF building blocks while supporting seamless verification across the design flow.

Qualifications

• Bachelor's degree in Electrical Engineering or related technical discipline required.
• 7+ years in design and development of fractional-N PLLs, DLLs, and sub-circuits in FinFET CMOS nodes (7nm+).
• Experience with PLL building blocks (VCOs, pre-scalers, PFDs, charge-pumps).

Responsibilities

• Own system and circuit design of PLLs and clock distribution in advanced CMOS tech, focusing on phase noise and power trade-offs.
• Use Spectre and AMS flows to develop high-performance PLL circuits.
• Collaborate with RF and SOC architects to define PLL requirements from system specs.
• Oversee layout, integration, floorplanning, and tape-out verification.
• Develop test plans with validation and product engineers for bring-up and high-yield production.
• Mentor junior engineers on analog design best practices.

Skills

Fractional-N PLLs

DLLs

VCO design

Clock distribution

Mixed-mode modeling

MATLAB

Spectre

SystemVerilog

AMS flows

PLL characterization

Analog/RF blocks

Education

Bachelor's degree in Electrical Engineering or related technical discipline

MS/PhD in Electrical Engineering (Preferred)

Tools

MATLAB

Spectre

SystemVerilog

AMS

Job description

Blue Origin seeks an IC Design Engineer to advance PLLs and clocking systems in cutting-edge CMOS processes. You will own system architecture, optimize phase noise and power, and collaborate with RF and SOC teams to meet stringent space-grade requirements.

You will mentor juniors, drive tape-out readiness, and contribute to robust analog/RF building blocks while supporting seamless verification across the design flow.