Senior Physical Design Methodology Engineer - PPA & Scaling

NVIDIA Corporation; Santa Clara (CA); Presencial; USD 168.000 - 311.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Equity

Benefits package

Descripción de la vacante

NVIDIA Corporation in Santa Clara, CA is seeking a Senior Physical Design Methodology Engineer to advance PPA improvement and technology scaling for GPUs and SOCs. You will develop methods, run floorplanning, power/clock distribution, and timing analyses across multiple projects.

Preferred MS in ECE with 5+ years in PD engineering, strong EDA tool knowledge, and programming in Perl, Python, and C++. Equity and a comprehensive benefits package accompany a competitive, level-based salary.

Formación

• MS in Electrical or Computer Engineering (or equivalent experience).
• Minimum 5 years’ experience in Physical Design Engineering.
• Familiar with Floor planning, Clock/Power distribution, Place & Route, Integration and Verification.
• Experience with Physical Design related to CPU designs is a plus.
• Strong background with hierarchical design approach, top-down design, budgeting, timing and physical convergence.
• Familiar with design-for-yield, manufacturability, EM/IR closure and thermal management.
• Expertise in industry standard EDA tools.
• Proficiency in programming and scripting languages, such as Perl, Python, and C++.

Responsabilidades

• Developing physical design methodologies for implementation of graphics processors and SOCs.
• Develop unique and creative solutions to state-of-the-art physical design problems for NVIDIA chips.
• Participate in PPA experiments, testing and developing new technologies across multiple projects (floorplanning, power/clock, P&R, timing, back-end verification).
• Develop automation to solve early design collaterals (scripts for library cells analysis, design constraint modifications).

Conocimientos

Perl

Python

C++

Educación

MS in Electrical or Computer Engineering

Herramientas

EDA tools

Descripción del empleo

NVIDIA Corporation in Santa Clara, CA is seeking a Senior Physical Design Methodology Engineer to advance PPA improvement and technology scaling for GPUs and SOCs. You will develop methods, run floorplanning, power/clock distribution, and timing analyses across multiple projects.

Preferred MS in ECE with 5+ years in PD engineering, strong EDA tool knowledge, and programming in Perl, Python, and C++. Equity and a comprehensive benefits package accompany a competitive, level-based salary.