Senior PD Methodology Engineer: PPA & Scaling

NVIDIA Corporation; Austin (TX); Presencial; USD 168.000 - 311.000; Jornada completa

Descripción de la vacante

NVIDIA Corporation is seeking a Senior Physical Design Methodology Engineer specializing in PPA improvement technology scaling. You will shape methodologies for graphic processors and SOCs, crafting innovative solutions and driving end-to-end physical design optimization across multiple projects.

You will participate in chip floorplanning, power and clock distribution, timing analysis and back-end verification, while developing automation to accelerate design constraints and cell analyses.

Formación

• MS in Electrical or Computer Engineering (or equivalent experience).
• 5+ years of experience in Physical Design Engineering.
• Familiar with Floor planning, Clock and Power distribution, Place and Route, Integration and Verification.
• Experience with Physical Design related to CPU designs is a plus.
• Strong background with hierarchical design approach, top-down design, budgeting, timing and physical convergence.
• Expertise with industry-standard EDA tools.

Responsabilidades

• Develop physical design methodologies for implementation of graphics processors and SOCs.
• Develop unique solutions to state-of-the-art physical design problems for NVIDIA chips.
• Participate in PPA experiments across CPUs/GPUs including floorplanning, power/clock, timing analysis and back-end verification.
• Develop automation scripts for design analysis and constraint modifications.

Conocimientos

Perl

Python

C++

Hierarchical design

Top-down design

Budgeting

Timing closure

Physical convergence

CPU/SoC design familiarity

Educación

MS in Electrical or Computer Engineering

Equivalent experience

Herramientas

EDA tools

Descripción del empleo

NVIDIA Corporation is seeking a Senior Physical Design Methodology Engineer specializing in PPA improvement technology scaling. You will shape methodologies for graphic processors and SOCs, crafting innovative solutions and driving end-to-end physical design optimization across multiple projects.

You will participate in chip floorplanning, power and clock distribution, timing analysis and back-end verification, while developing automation to accelerate design constraints and cell analyses.