Senior Physical Design Engineer - Low-Power SoC

Innophaseiot; San Diego (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Innophase IoT in California is seeking a Physical Design Principal Engineer to own the entire RTL-to-GDS flow for a low-power SOC, including floorplanning, place&route, CTS, STA, and signoff. You’ll join a team delivering advanced wireless semiconductor platforms in a fabless environment.

The role requires 10+ years in physical design or 15+ years with a bachelor’s, and strong Cadence tool experience. Located in San Diego or San Jose, CA for on-site collaboration and execution.

Qualifications

• Master’s degree or above in electrical/computer engineering with 10+ years of experience, or bachelor’s with 15+ years.
• Strong experience in Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification.
• End-to-end RTL-to-GDS flow including full-chip floorplan, place-and-route, CTS, and layout verification for low-power SoCs.
• Netlist or RTL-to-GDS physical implementation experience.
• Deep knowledge of major EDA tools and Cadence workflows.
• Experience with TSMC N22 or below technology.
• Chip integration and signoff experience.
• Perl and TCL scripting proficiency.

Responsibilities

• Complete entire physical implementation of the block and chip level.
• Perform synthesis and physical implementation steps – synthesis, floor-planning, power delivery, place & route, timing noise, physical verification, IR/RV.
• Collaborate with the SOC design team to drive architectural feasibility studies, target timing/power/area, and RTL/design tradeoffs.
• Analyze the quality of the floorplan and Clock tree structure and Place & Route.
• Implement ECOs for timing closure.
• Signal EM/Noise and Power/IR/EM analysis and fixes.
• DRC/LVS/ERC/ANTENNA analysis and cleanup.
• Timing verification and signoff.
• Physical verification and sign-off.

Skills

RTL-to-GDS flow

Physical design

Cadence tools

Power/ground grids

Timing ECO

Netlist-GDS flow

RTL-Verilog/VHDL

Perl/TCL scripting

Education

Master's degree in electrical/computer engineering

Bachelor's degree in electrical/computer engineering

Tools

Cadence Design Systems

Job description

Innophase IoT in California is seeking a Physical Design Principal Engineer to own the entire RTL-to-GDS flow for a low-power SOC, including floorplanning, place&route, CTS, STA, and signoff. You’ll join a team delivering advanced wireless semiconductor platforms in a fabless environment.

The role requires 10+ years in physical design or 15+ years with a bachelor’s, and strong Cadence tool experience. Located in San Diego or San Jose, CA for on-site collaboration and execution.