Principal Engineer, Physical Design

Innophaseiot; San Diego (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Innophase IoT in California is seeking a Physical Design Principal Engineer to own the entire RTL-to-GDS flow for a low-power SOC, including floorplanning, place&route, CTS, STA, and signoff. You’ll join a team delivering advanced wireless semiconductor platforms in a fabless environment.

The role requires 10+ years in physical design or 15+ years with a bachelor’s, and strong Cadence tool experience. Located in San Diego or San Jose, CA for on-site collaboration and execution.

Qualifications

• Master’s degree or above in electrical/computer engineering with 10+ years of experience, or bachelor’s with 15+ years.
• Strong experience in Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification.
• End-to-end RTL-to-GDS flow including full-chip floorplan, place-and-route, CTS, and layout verification for low-power SoCs.
• Netlist or RTL-to-GDS physical implementation experience.
• Deep knowledge of major EDA tools and Cadence workflows.
• Experience with TSMC N22 or below technology.
• Chip integration and signoff experience.
• Perl and TCL scripting proficiency.

Responsibilities

• Complete entire physical implementation of the block and chip level.
• Perform synthesis and physical implementation steps – synthesis, floor-planning, power delivery, place & route, timing noise, physical verification, IR/RV.
• Collaborate with the SOC design team to drive architectural feasibility studies, target timing/power/area, and RTL/design tradeoffs.
• Analyze the quality of the floorplan and Clock tree structure and Place & Route.
• Implement ECOs for timing closure.
• Signal EM/Noise and Power/IR/EM analysis and fixes.
• DRC/LVS/ERC/ANTENNA analysis and cleanup.
• Timing verification and signoff.
• Physical verification and sign-off.

Skills

RTL-to-GDS flow

Physical design

Cadence tools

Power/ground grids

Timing ECO

Netlist-GDS flow

RTL-Verilog/VHDL

Perl/TCL scripting

Education

Master's degree in electrical/computer engineering

Bachelor's degree in electrical/computer engineering

Tools

Cadence Design Systems

Job description

About InnoPhase IoT

If you are keen to work with a bunch of brilliant people with various backgrounds, if you share the same value of working smart and celebrating successes, if you have enthusiasm for big technology in a small company, if your goals are to learn and experience different aspects of work--not just singing the same song every day, you’ll find your playground at Innophase IoT.

We are looking for people seeking AWESOMENESS! If you’re good at what you do, you can work anywhere. If you’re the best at what you do, come work at Innophase IoT!

Overview of Role

As a Physical Design Principal Engineer, you will be responsible for the entire SOC implementation and verification flow from RTL-to-GDS that includes floorplan, place and route, CTS, STA,PV/EMIR/Noise/SigEM cleanup and signoffon lower power SoC. You will be joining a team of engineers dedicated to pushing the envelope for a leading fabless wireless semiconductor platform company specializing in extreme low power wireless radio solutions.

Location

• San Diego or San Jose, CA

Responsibilities

• Complete entire physical implementation of the block and chip level
• Perform synthesis and physical implementation steps – synthesis, floor-planning, power delivery, place&route, timing noise, physical verification, IR/RV.
• Collaborate with the SOC design team to drive architectural feasibility studies, develop timing, power, and area design targets, and explore RTL/design tradeoffs
• Analyze the quality of the floorplan and CustomizedClock tree structure and Place & Route
• Implement ECOs for timing closure
• Signal EM/Noise and PowerIR/EM analysis and fix
• DRC/LVS/ERC/ANTENNA analysis and clean up
• Timing verification and signoff
• Physical verification and sign off

Minimum Qualifications

• Master’s degree or above in electrical/computer science engineering with 10+ years of industry experience, or bachelor’s degree in electrical/computer science engineering plus 15+ years of industry experience
• Strong experience in Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification.
• The entire SOC implementation and verification flow from RTL-to-GDS that includes fullchip floorplan, place and route, CTS, and layout verification signoff on lower power SoC
• Netlist (or RTL)-GDS physical implementation experience
• In depth knowledge of major EDA tools/design flows
• Strong Cadence experience/background
• Experience with TSMC N22 or below technology
• Experience in chip integration and signoff
• Experience in Perl/TCL language programming

Preferred Qualifications

• Strong experience in Low-power implementation methodology
• Strong experience in Advanced timing signoff methodology
• Knowledge of DFT (BSCAN, MBIST, SCAN) and understanding of their impact on physical design flows
• Able to independently complete Netlist-GDS P&R, signoff task
• Proven record in multi-million gate design production tapeouts

It is key to unleash the potential in every employee, every team, every leader, and the company herself. We know employees perform best when motivated, appreciated and recognized, and can be themselves. We are committed to building a culture where every voice can be heard, everyone has room for growth and can make meaningful contributions. At the end of the day, we want success not just for the company, but also for everyone who believes in the company, the vision, and the future.