Senior Physical Design Engineer, FPGA/SoC (San Jose)

Altera Corporation; San Jose (CA); Presencial; USD 133.000 - 193.000; Jornada completa

Descripción de la vacante

Altera Corporation is seeking a Senior Physical Design Engineer in San Jose, CA to lead physical implementation of IP/SoC from RTL to GDSII and drive timing closure, power optimization, and design sign-off for next‑gen FPGA products.

You will collaborate with RTL, CAD, and verification teams to deliver high‑quality silicon while improving physical design methodologies and automation. A strong background in CTS, STA, and multi‑domain design is required.

Formación

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical discipline.
• 6+ years of hands-on experience with digital ASIC or SoC physical design implementation.
• 6+ years RTL-to-GDSII physical design flows.
• 6+ years of experience with synthesis, floorplanning, place and route, and clock tree synthesis (CTS).
• 6+ years of experience performing static timing analysis (STA) and timing closure.
• 4+ years of experience with physical verification, including DRC, LVS, ERC, and sign-off methodologies.
• 4+ years of experience using industry-standard physical design EDA tools such as Synopsys Fusion Compiler, ICC2, PrimeTime, Cadence Innovus, or equivalent.
• 3+ years of experience optimizing designs for power, performance, and area (PPA).
• 2+ years of experience supporting designs with multiple voltage or power domains.

Responsabilidades

• Perform physical design implementation of custom IP and SoC designs from RTL through GDSII to create a manufacturing-ready design database.
• Execute all aspects of the physical design flow, including synthesis, floorplanning, place and route, CTS, static timing analysis (STA), power and clock distribution, reliability analysis, and power/noise analysis.
• Perform physical verification and design signoff, including formal equivalence checking, static timing verification, reliability verification, power integrity analysis, layout verification, ERC, and structural design checking.
• Analyze implementation and signoff results, identify violations, and develop solutions that improve current and future product architectures.
• Apply expertise in physical clock design, timing closure, placement, routing, synthesis, DFT implementation, multiple power domain analysis, and coverage analysis using industry-standard EDA tools.
• Optimize physical designs to improve power, performance, frequency, and area (PPA).
• Collaborate with cross-functional engineering teams to resolve implementation challenges throughout the design cycle.
• Participate in the development and continuous improvement of physical design methodologies, design flows, and automation.

Conocimientos

Digital ASIC design

RTL-to-GDSII

Physical verification

Timing closure

PPA optimization

EDA tools

Educación

Bachelor's in Electrical Engineering/Computer Engineering/Computer Science

Herramientas

Synopsys Fusion Compiler

ICC2

PrimeTime

Cadence Innovus

Descripción del empleo

Altera Corporation is seeking a Senior Physical Design Engineer in San Jose, CA to lead physical implementation of IP/SoC from RTL to GDSII and drive timing closure, power optimization, and design sign-off for next‑gen FPGA products.

You will collaborate with RTL, CAD, and verification teams to deliver high‑quality silicon while improving physical design methodologies and automation. A strong background in CTS, STA, and multi‑domain design is required.