PD Engineer

Carman Solutions Group; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Carman Solutions Group in Sunnyvale, CA is seeking a Senior Physical Design Engineer with 8–14 years of hands-on RTL to GDSII implementation for low power SoCs on advanced nodes.

The role emphasizes Fusion Compiler expertise, UPF-based power optimizations, and end-to-end flow leadership across synthesis, floorplanning, placement, CTS, routing and timing closure. You will mentor juniors and drive automation with TCL, Python and Shell.

Qualifications

• 8–14 years hands-on physical design experience.
• Expertise in Fusion Compiler, low power design and PPA optimization.
• Strong scripting skills in Tcl, Python and Shell.
• Solid understanding of SoC hierarchy, signoff flows, and constraint management.
• Excellent problem solving, communication and leadership abilities.

Responsibilities

• Drive physical design flow: synthesis, floorplanning, placement, CTS, routing, timing closure.
• Deliver low power designs using UPF methodologies on advanced nodes.
• Resolve SoC integration challenges including SDC constraints and UPF promotion.
• Develop and maintain automation flows with Tcl, Python and Shell; collaborate with cross-functional teams.
• Mentor and lead junior team members and contribute to flow improvements.

Skills

Fusion Compiler

Low Power Design

PPA Optimization

Scripting Tcl

Python

Shell

SoC hierarchy

Constraint management

Leadership

Debugging

Education

B.Tech/M.Tech in ECE, EE, or VLSI

Tools

PT signoff

ICV signoff

Job description

Visa- G C and U S C Only

We are looking for a Senior Physical Design Engineer with 8–14 years of experience to lead and execute RTL to GDSII implementation for low power SoCs on advanced nodes.

Senior Physical Design Engineer

Sunnyvale, CA, USA

Fulltime

Visa- G C and U S C Only

We are looking for a Senior Physical Design Engineer with 8–14 years of experience to lead and execute RTL to GDSII implementation for low power SoCs on advanced nodes.

This role demands deep expertise in Synopsys Fusion Compiler, strong scripting and automation, and a proven track record of achieving best-in-class PPA.

What You Will Do

• Drive physical design flow: synthesis, floorplanning, placement, CTS, routing, timing closure.


• Deliver low power designs using advanced UPF methodologies on 5nm/3nm nodes.


• Resolve SoC/SS integration challenges including SDC constraints and UPF promotion/pushdown.


• Develop and maintain automation flows using Tcl, Python, and Shell. Collaborate with cross-functional teams for design closure and signoff. Mentor and lead junior team members.


• Innovate and contribute to flow/methodology improvements.

What You Will Bring

• B.Tech/M.Tech in ECE, EE, or VLSI.


• 8–14 years hands-on physical design experience.


• Expert in Fusion Compiler, low power design, and PPA optimization. Strong scripting skills (Tcl/Python/Shell).


• Good understanding of SoC hierarchy, signoff flows, and constraint management. Excellent problem-solving, communication, and leadership skills.

Preferred

Experience in top-level SoC integration, signoff tools (PT, ICV), and DFM checks.

Experience :10+years