Senior Physical Design Engineer

Vastika Inc; Sunnyvale (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Vastika Inc. is seeking a Senior Physical Design Engineer with 8–14 years of experience to lead RTL to GDSII implementation for low power SoCs on advanced nodes. The role requires deep expertise in Synopsys Fusion Compiler, strong scripting and automation, and a proven track record of achieving best-in-class PPA.

You will deliver low power designs, resolve integration challenges, develop automation flows, and mentor junior engineers while contributing to flow improvements.

Qualifications

• 8–14 years hands-on physical design experience.
• Expertise in Fusion Compiler, low power design, and PPA optimization.
• Strong scripting skills (Tcl/Python/Shell).
• Good understanding of SoC hierarchy, signoff flows, and constraint management.
• Excellent problem-solving, communication, and leadership skills.

Responsibilities

• Deliver low power designs using advanced UPF methodologies on 5nm/3nm nodes.
• Resolve SoC/SS integration challenges including SDC constraints and UPF promotion/pushdown.
• Develop and maintain automation flows using Tcl, Python, and Shell. Collaborate with cross-functional teams for design closure and signoff. Mentor and lead junior team members.
• Innovate and contribute to flow/methodology improvements.

Skills

Leadership

Communication

Problem-solving

Mentoring

Education

B.Tech./M.Tech in ECE/EE/VLSI

Tools

Synopsys Fusion Compiler

UPF

Python

Tcl

Shell

Job description

Company Description Vastika Inc. is a global workforce solutions organization incorporated in the USA, specializing in IT, Engineering, Project Management, Healthcare staffing, and staff augmentation. The company focuses on connecting organizations with top-tier talent across industries through tailored staffing solutions that streamline hiring and support business growth. Vastika’s experienced team partners with Fortune 1000 companies, leveraging a diverse talent pool that spans entry-level to executive roles. With strong industry expertise, customized placement strategies, and a rigorous screening process, Vastika delivers high-quality candidates for temporary, permanent, and contract roles. Its global reach and commitment to understanding client needs make Vastika a trusted partner in recruitment and workforce innovation.

We are looking for a Senior Physical Design Engineer with 8–14 years of experience to lead and execute RTL to GDSII implementation for low power SoCs on advanced nodes.

This role demands deep expertise in Synopsys Fusion Compiler, strong scripting and automation, and a proven track record of achieving best-in-class PPA.

What You will Do:

• Deliver low power designs using advanced UPF methodologies on 5nm/3nm nodes.
• Resolve SoC/SS integration challenges including SDC constraints and UPF promotion/pushdown.
• Develop and maintain automation flows using Tcl, Python, and Shell. Collaborate with cross-functional teams for design closure and signoff. Mentor and lead junior team members.
• Innovate and contribute to flow/methodology improvements.

What You Will Bring:

• B.Tech/M.Tech in ECE, EE, or VLSI.
• 8–14 years hands-on physical design experience.
• Expert in Fusion Compiler, low power design, and PPA optimization. Strong scripting skills (Tcl/Python/Shell).
• Good understanding of SoC hierarchy, signoff flows, and constraint management. Excellent problem-solving, communication, and leadership skills.

Preferred:

• Experience in top-level SoC integration, signoff tools (PT, ICV), and DFM checks.