Senior Physical Design Engineer

Infobahn Softworld Inc; Sunnyvale (CA); On-site; USD 200,000 - 250,000; Full time

Job summary

An established industry player is seeking a skilled Physical Design Engineer to join their dynamic team. This role offers the opportunity to work on cutting-edge projects, focusing on high-quality tape-out execution. You will leverage your expertise in Synopsys tools and methodologies to ensure successful design closure and verification. Collaborating with a talented group of professionals, you will tackle complex challenges in the realm of SOC implementation and physical design, making a significant impact in the software development and computer hardware manufacturing sectors. If you're passionate about engineering and eager to contribute to innovative solutions, this position is perfect for you.

Qualifications

• 10+ years of experience in Physical Design Engineering with a focus on high-quality tape-out.
• Solid track record in executing complex IP Sub-Systems like PCIe, USB, and DDR.

Responsibilities

• Manage the physical design process including synthesis, DFT insertion, and timing closure.
• Collaborate with teams to ensure high-quality standards for tape-out delivery.

Skills

Synopsys Fusion Compiler

Physical Design Engineering

DFT insertion

Place & Route

Timing Closure

RTL handover

SOC implementation methodologies

SDC STA constraints development

Ansys Redhawk SC

DFT experience

Tools

Synopsys DC

Synopsys ICV

Synopsys Formality

GlobalFoundries technology nodes

TSMC technology nodes

Samsung technology nodes

Job description

Account Delivery Manager at Infobahn Softworld Inc

Job Title: Physical Design Engineer

Work Location: Sunnyvale, CA

The following are the general qualifications for the Physical Design Engineering position:

• Experience: 10yrs+
• Synopsys Fusion Compiler/ICC2 (Synthesis, DFT insertion, Place & Route, Chip Finishing, PT-SI STA, Timing Closure, PV (DRC/ERC/PERC/LVS)
• Synopsys DC, DCG, DC TOPO, and FC Synthesis a plus
• Synopsys Flow Development & SOC implementation methodologies that will be deployed and used by our Synopsys customer Physical Design Implementation team members
• Familiar with Synopsys Lynx a plus
• RTL handover experience a plus for RTL to GDS
• Experience with top-level floorplanning, bump-maps, RDL IO Pad/Ring creation/verification, power grid creation/verification, hierarchal floorplanning/partitioning
• Solid experience with full SOC clocking methodologies (H-Tree, Structure Clocking, MS CTS for Top/Blocks with push/down & bottoms up approaches)
• Highly proficient with SDC STA constraints development driving back-end tools for blocks and full-chip through timing closure & sign-off
• Ability to define and understand sign-off requirements/margins based on Foundry technology requirements a plus
• DFT experience with compression, scan, TDF, and MEMBIST a plus
• Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate) & Formality ECO flows
• Familiar with UPF flows & methodologies for multi-voltage power domains with turn on/turn off using UPF
• Synopsys ICV for PV (Physical Verification – DRC/ERC/LVS/PERC)
• Ansys Redhawk SC (For IR analysis for static, dynamic, & EMIR)
• Experience in PD implementation/design closure on complex IP Sub-Systems such as PCIe, USB, MIPI, DDR, & HBM a plus
• Experience with GlobalFoundries, TSMC, & Samsung technology nodes is a plus
• Consultants should have a solid track record on execution delivering to high-quality standards for delivering to high-quality tape-out

Seniority level

Mid-Senior level

Employment type

Contract

Job function

Engineering and Information Technology

Industries

Software Development and Computer Hardware Manufacturing