Design Verification Engineer

Acceler8 Talent; San Francisco (CA); Remote; USD 220,000 - 250,000; Full time

Job summary

Acceler8 Talent is seeking a Design Verification Engineer for a growing data center acceleration company in the San Francisco Bay Area. This role involves working on advanced interconnect architecture while offering a fully remote position. Candidates should have a strong background in SmartNIC and PCIe technologies and a minimum of 5 to 10 years of relevant experience in the semiconductor field.

Qualifications

• Minimum BSEE/CE + 10 years or MSEE/CE + 5 years experience.
• Proven track record of design execution and quality.
• Deep experience with full chip verification and infrastructure development.

Responsibilities

• Industry experience with SmartNIC and PCIe required.
• Experience with Ethernet and FPGA design verification preferred.
• Execute quality design on high-volume products.

Skills

CXL

PCIe

FPGA design flow

UVM constructs

SystemVerilog

Python

C/C++

Education

BSEE/CE

MSEE/CE

Job description

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This range is provided by Acceler8 Talent. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$220,000.00/yr - $250,000.00/yr

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Building North American Semiconductor and Photonic design teams

Acceler8 Talent has partnered with a well-supported data center acceleration company that is actively searching for a driven Design Verification Engineer.

This company is deeply committed to developing a novel interconnect architecture aimed at resolving congestion challenges within extensively distributed systems. Their recent successful completion of a significant Series B funding round serves as a strong indicator of their growth and potential.

The company's founding members bring substantial expertise from distinguished hardware and technology enterprises. Notably, their primary investor boasts an admirable track record of nurturing early-stage startups into prosperous and thriving enterprises.

They are currently seeking an engineer with a high level of expertise with SmartNIC and or Switch Verification, PCIe Serdes/PHY, or Ethernet Serdes/PHY.

If you are located in the San Francisco Bay Area, Austin, TX, Raleigh, NC, or Boston, MA, area this company is offering a fully remote position.

Requirements

• Proven industry experience with CXL and or PCIe
• Industry experience with Ethernet.
• Experience with FPGA design flow/verification is a strong advantage.
• Deep experience with full chip verification and infrastructure development.
• Strong current knowledge of UVM constructs, components, and practices.
• Expert knowledge of SystemVerilog, as well as Python or other scripting languages.
• Experience with C/C++ and general software engineering principles is highly desirable.
• Minimum BSEE/CE + 10 years or MSEE/CE + 5 years experience.
• Proven track record of design execution and quality on products which have shipped in high-volume.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Industries

  Semiconductor Manufacturing and Computer Hardware Manufacturing

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