Senior Physical Design Engineer

NVIDIA Corporation; Santa Clara (CA); On-site; USD 136,000 - 218,500; Full time

Job summary

NVIDIA Corporation is seeking a Senior Physical Design Engineer located in Santa Clara, California. The successful candidate will drive physical design and timing, partner with mixed signal teams, and perform physical verification checks. Candidates should possess a BS or MS in Electrical or Computer Engineering and have relevant experience in physical design and timing tools such as Synopsys or Cadence. The position offers a base salary ranging from $136,000 to $264,500 depending on experience and level.

Qualifications

• 5+ years of experience in physical design with a BS or 2+ years with an MS.
• Experience in place and route tools.
• Ability to automate flows and form methodologies.

Responsibilities

• Drive physical design and timing from netlist to GDS.
• Partner with mixed signal teams to integrate Analog IOs and macros.
• Perform physical verification checks.

Skills

Physical design

Timing closure

Analog integration

Synopsys/Cadence tools

Debugging timing violations

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Tools

Synopsys

Cadence

Job description

## Senior Physical Design EngineerApplylocations: US, CA, Santa Claratime type: Full timeposted on: Posted Yesterdayjob requisition id: JR2017826We are now looking for a motivated Physical Design Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, join us today! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing!More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities which are hard to tackle, that only we can pursue, and that matter to the world. This is our life's work, to amplify human inventiveness and intelligence.**What you'll be doing:*** Drive physical design and timing from netlist to gds.* Partner with mixed signal teams to integrate Analog IO’s and macros.* Work on multi-mode and multi-corner timing closure, RC extraction, Cross talk, IR drop and EM analysis.* Work with the Front-end teams to create and update timing constraints.* Perform Physical verification DRC, ERC, LVS, Antenna checks and other checks.* Debugging timing violations and implementing functional, Timing ECO’s and perform formal verification.**What we need to see:*** BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years' experience or MS (or equivalent experience) with 2+ years' experience in physical design.* Experienced in Synopsys or Cadence place and route, physical design and timing tools.* Ability to form methodologies and automate flows.* Scan insertion and DFT knowledge is a plusYour base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until May 16, 2026.This posting is for an existing vacancy.NVIDIA uses AI tools in its recruiting processes.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.