Senior Physical Design Engineer

NVIDIA Gruppe

Westford (MA)

On-site

USD 136,000 - 218,500

Full time

14 days+

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Benefits offered by this job

Equity options
Comprehensive benefits package

Job summary

NVIDIA Gruppe in Westford, Massachusetts is seeking a talented engineer to lead physical design for SOC devices targeted at the networking markets. The role requires strong VLSI design skills and expertise in state-of-the-art technologies.

The ideal candidate has over 5 years of experience in physical design, proficiency with Synopsys and Cadence tools, and excellent teamwork skills. A base salary range of $136,000 to $264,500 available based on level and experience.

Qualifications

  • 5 years of experience in VLSI physical design implementation on 5nm, 4nm and 3nm technology.
  • A successful track record of delivering designs to production.
  • Validated strong power user of P&R, Timing Analysis, and Physical Verification.

Responsibilities

  • Lead all aspects of physical design and implementation of SOC devices.
  • Participate in establishing physical design methodologies and flow automation.
  • Perform daily tasks involved in physical chip development.

Skills

VLSI physical design
Power/clock distribution
Timing closure
Python
Teamwork

Education

BSEE / MSEE or equivalent experience

Tools

Synopsys tools
Cadence tools

Job description

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

What you’ll be doing:
  • Lead all aspects of physical design and implementation of SOC devices targeted at the networking markets.
  • Work at the partition and chiplet level.
  • Participate as a team member in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure.
  • Perform daily tasks involved in physical chip development (RTL2GDS), including trial synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
What we need to see:
  • BSEE / MSEE or equivalent experience.
  • 5 years of experience in VLSI physical design implementation on 5nm, 4nm and 3nm technology.
  • A successful track record of delivering designs to production is a requirement.
  • Ability to assist in design flow development and debugging, including application of ML/AI solutions.
  • Validated strong power user of P&R, Timing Analysis, Physical Verification, IR Drop Analysis, CAD tools from Synopsys (ICC2/DC/PT/STAR/ICV), Cadence (Genus/Innovus/Tempus) and other major EDA companies.
  • Confirmed prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/route and tapeout solutions.
  • Strong analytical and debugging skills.
  • Proficiency using Python, Perl, Tcl, Make scripting is helpful.
  • Excellent teamwork abilities.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until April 19, 2026.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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