Senior Mask Design Engineer – Hardware

NVIDIA Corporation; Santa Clara (CA); Remote; USD 168,000 - 259,000; Full time

Job summary

NVIDIA is seeking a Senior Mask Design Engineer to contribute to the detailed layout of silicon interposers for NVIDIA products. You will collaborate with PTL and I/O signal integrity teams to deliver tight-schedule packages using Cadence tools.

The role requires a BS in Electrical Engineering, 5+ years of mask/layout experience, deep CMOS layout knowledge, and Cadence Virtuoso expertise, plus scripting and verification tool familiarity.

Qualifications

• Hold a B.S. Electrical Engineering or equivalent experience.
• Minimum of 5+ years proven experience in Mask and Layout Design.
• Deep understanding of layout concepts in submicron CMOS technologies.
• You are an authority with Cadence layout tools - particularly Virtuoso.
• Knowledge of Integrity auto-routing is a plus.
• Experience running and debugging with verification tools such as Calibre, ICV, Thunder, etc.
• Proficient in scripting languages like Perl, Python, Skill, etc.
• Should have knowledge of DRC and LVS checking flows, ability to customize decks.
• Knowledge of APD package layout tool is a plus.
• Good understanding of packaging technology is useful.
• You can work optimally in a team, good interpersonal skills, passion and positive energy.

Responsibilities

• Collaborate cross functionally with PTL and I/O signal integrity and technology engineers to deliver solution for product packages in tight schedule.
• Perform physical layout for silicon interposer using Cadence tools.
• Conduct design feasibility studies to evaluate the package design goals for size, cost, and system performance.
• Take part in studying layout floorplan and perform custom layout and verification against design rules and netlists.
• Propose layout design trade-offs to the PTL for resolution and implementation.

Skills

Strong teamwork

Good interpersonal skills

Problem solving

Automation scripting experience

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence Virtuoso

Integrity auto-routing

Calibre

ICV

Thunder

Perl

Python

Skill (Cadence)

APD package layout tool

Job description

## Senior Mask Design Engineer – HardwareApplylocations: US, CA, Santa Clara: US, NV, Remote: US, OR, Remote: US, AZ, Remote: US, WA, Remotetime type: Full timeposted on: Posted Todayjob requisition id: JR2022912NVIDIA’s GPUs and SOCs are the world leaders in power, performance, and efficiency. We are continually innovating to deliver new and creative, unusual solutions to extraordinary problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Mask Design Engineer who is committed to making a difference in the world through their contributions!This position will collaborate with Package Technical Lead and different design teams in designing and developing sophisticated, detailed layout of silicon interposers for NVIDIA products. In addition, work with design teams to plan schedules, resolve costs, manufacturing, and electrical design issues.**What you'll be doing:*** You'll collaborate cross functionally with package technical lead (PTL) and I/O signal integrity and technology engineers to deliver solution for product packages in tight schedule.* Performing physical layout for silicon interposer using Cadence tools.* Conduct design feasibility studies to evaluate the package design goals for size, cost, and system performance.* Take part in studying layout floorplan and perform custom layout and verification against design rules and netlists.* Propose layout design trade-offs to the PTL for resolution and implementation.**What we need to see:*** Hold a B.S. Electrical Engineering or equivalent experience* Minimum of 5+ years proven experience in Mask and Layout Design.* Deep understanding of layout concepts in submicron CMOS technologies.* You are an authority with Cadence layout tools - particularly Virtuoso.* Knowledge of Integrity auto-routing is a plus.* Experience running and debugging with verification tools such as Calibre, ICV, Thunder, etc.* Proficient in scripting languages like Perl, Python, Skill, etc.* Should have knowledge of DRC and LVS checking flows, ability to customize decks.* Knowledge of APD package layout tool is a plus.* Good understanding of packaging technology is useful.* You can work optimally in a team, good interpersonal skills, passion and positive energy.NVIDIA is widely considered to be one of the technology world’s most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you#LI-HybridYour base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 258,750 USD for Level 4.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until August 10, 2026.This posting is for an existing vacancy.NVIDIA uses AI tools in its recruiting processes.NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.